Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
266
Note: The transaction-complete interrupts are triggered when both single and burst transactions are complete. The same
transaction-complete interrupt is used for both single and burst transactions.
24.3.3.2 Hardware Handshaking
There are five hardware handshaking interfaces connected to four external DMA requests (see Table 24-1).
External DMA Request Definition
When an external slave peripheral requires the DMAC to perform DMA transactions, it communicates its request
by asserting the external nDMAREQx signal. This signal is resynchronized to ensure a proper functionality (see
Figure 24-4).
The external nDMAREQx is asserted when the source threshold level is reached. After resynchronization, the
rising edge of dma_req starts the transfer. dma_req is de-asserted when dma_ack is asserted.
Each DMAREQx assertion leads to a transfer. Its size (given by CTLxL.SRC_MSIZE and CTLxL.DEST_MSIZE) is
decremented from CTLxH.BLOCK_TS.
The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted again before a new
transaction starts. The DMA ends the current transfer.
For a source FIFO, an active edge is triggered on nDMAREQx when the source FIFO exceeds a watermark level.
For a destination FIFO, an active edge is triggered on nDMAREQx when the destination FIFO drops below the
watermark level.
The source transaction length, CTLxL.SRC_MSIZE, and destination transaction length, CTLxL.DEST_MSIZE,
must be set according to watermark levels on the source/destination peripherals.
Figure 24-4. External DMA Request Timing
Table 24-1. Hardware Handshaking Connection
Request Definition Hardware Handshaking Interface
DMAREQ0 External DMA Request 0 1
DMAREQ1 External DMA Request 1 2
DMAREQ2 External DMA Request 2 3
DMAREQ3 External DMA Request 3 4
DMA Transfers DMA Transfers
Hclk
nDMAREQx
dma_req
dma_ack
DMA Transfers
DMA Transaction