Datasheet

265
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.3.3 Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. The
operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow
controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over
the AMBA bus. A non-memory peripheral can request a DMA transfer through the DMAC using one of two
handshaking interfaces:
 Hardware handshaking
 Software handshaking
Software selects between the hardware or software handshaking interface on a per-channel basis. Software
handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished
using a dedicated handshaking interface.
24.3.3.1 Software Handshaking
When the slave peripheral requires the DMAC to perform a DMA transaction, it communicates this request by
sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMA transaction. These
software registers are used to implement the software handshaking interface.
The HS_SEL_SRC/HS_SEL_DST bit in the DMAC_CFGx channel configuration register must be set to enable
software handshaking.
When the peripheral is not the flow controller, then the last transaction registers DMAC_LstSrcReg and
DMAC_LstDstReg are not used, and the values in these registers are ignored.
Burst Transactions
Writing a 1 to the DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] register is always interpreted as a burst transaction
request, where x is the channel number. However, in order for a burst transaction request to start, software must
write a 1 to the DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] register.
You can write a 1 to the DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] and
DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers in any order, but both registers must be asserted in order to
initiate a burst transaction. Upon completion of the burst transaction, the hardware clears the
DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] and DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers.
Single Transactions
Writing a 1 to the DMAC_SglReqSrcReg/DMAC_SglReqDstReg initiates a single transaction. Upon completion of
the single transaction, both the DMAC_SglReqSrcReg/DMAC_SglReqDstReg and
DMAC_ReqSrcReg/DMAC_ReqDstReg bits are cleared by hardware. Therefore, writing a 1 to the
DMAC_ReqSrcReg/DMAC_ReqDstReg is ignored while a single transaction has been initiated, and the requested
burst transaction is not serviced.
Again, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg register is always a burst transaction request.
However, in order for a burst transaction request to start, the corresponding channel bit in the
DMAC_SglReqSrcReg/DMAC_SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is
serviced, you must write a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg before writing a 1 to the
DMAC_SglReqSrcReg/DMAC_SglReqDstReg register.
Software can poll the relevant channel bit in the DMAC_SglReqSrcReg/ DMAC_SglReqDstReg and
DMAC_ReqSrcReg/DMAC_ReqDstReg registers. When both are 0, then either the requested burst or single
transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled and unmasked in
order to generate an interrupt when the requested source or destination transaction has completed.