Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
264
Single-block DMA transfer: Consists of a single block.
Multi-block DMA transfer: A DMA transfer may consist of multiple DMAC blocks. Multi-block DMA transfers are
supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks.
The source and destination can independently select which method to use.
 Linked lists (block chaining) – A linked list pointer (LLP) points to the location in system memory
where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next block
(block descriptor) and an LLP register. The DMAC fetches the LLI at the beginning of every block
when block chaining is enabled.
 Auto-reloading – The DMAC automatically reloads the channel registers at the end of each block to
the value when the channel was first enabled.
 Contiguous blocks – Where the address between successive blocks is selected to be a continuation
from the end of the previous block.
Scatter: Relevant to destination transfers within a block. The destination AMBA address is
incremented/decremented by a programmed amount when a scatter boundary is reached. The number of AMBA
transfers between successive scatter boundaries is under software control.
Gather: Relevant to source transfers within a block. The source AMBA address is incremented/decremented by a
programmed amount when a gather boundary is reached. The number of AMBA transfers between successive
gather boundaries is under software control.
Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for
the master bus interface for the duration of a DMA transfer, block, or transaction (single or burst).
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hlock for the
duration of a DMA transfer, block, or transaction (single or burst). Channel locking is asserted for the duration of
bus locking at a minimum.
FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the FIFO is less than half
full to fetch the data from the source peripheral and waits until the FIFO is greater than or equal to half full to send
data to the destination peripheral. Thus, the channel can transfer the data using AMBA bursts, eliminating the
need to arbitrate for the AHB master interface for each single AMBA transfer. When this mode is not enabled, the
channel only waits until the FIFO can transmit/accept a single AMBA transfer before requesting the master bus
interface.
Pseudo fly-by operation: Typically, it takes two AMBA bus cycles to complete a transfer, one for reading the
source and one for writing to the destination. However, when the source and destination peripherals of a DMA
transfer are on different AMBA layers, it is possible for the DMAC to fetch data from the source and store it in the
channel FIFO at the same time as the DMAC extracts data from the channel FIFO and writes it to the destination
peripheral. This activity is known as pseudo fly-by operation. For this to occur, the master interface for both source
and destination layers must win arbitration of their AHB layer. Similarly, the source and destination peripherals
must win ownership of their respective master interfaces.
24.3.2 Memory Peripherals
Figure 24-3 on page 263 shows the DMA transfer hierarchy of the DMAC for a memory peripheral. There is no
handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once
the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative
to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the
peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus.
By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data,
and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.