Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
262
24.3 Functional Description
24.3.1 Basic Definitions
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the
channel FIFO. The source peripheral teams up with a destination peripheral to form a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the
source peripheral).
Memory: Source or destination that is always “ready” for a DMA transfer and does not require a handshaking
interface to interact with the DMAC. A peripheral should be assigned as memory only if it does not insert more than
16 wait states. If more than 16 wait states are required, then the peripheral should use a handshaking interface
(the default if the peripheral is not programmed to be memory) in order to signal when it is ready to accept or
supply data.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination
peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is
not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not
memory, then a destination handshaking interface is assigned to the channel. Source and destination
handshaking interfaces can be assigned dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination
over the AHB bus.
Slave interface: The AHB interface over which the DMAC is programmed. The slave interface in practice could be
on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC
and source or destination peripheral to control the transfer of a single or burst transaction between them. This
interface is used to request, acknowledge, and control a DMAC transaction. A channel can receive a request
through one of three types of handshaking interface: hardware, software, or peripheral interrupt.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or burst transaction
between the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or burst transaction
between the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed
on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without
modifying it.
Peripheral interrupt handshaking interface: A simple use of the hardware handshaking interface. In this mode,
the interrupt line from the peripheral is tied to the dma_req input of the hardware handshaking interface. Other
interface signals are ignored.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines the length of and
terminates a DMA block transfer. If the length of a block is known before enabling the channel, then the DMAC
should be programmed as the flow controller. If the length of a block is not known prior to enabling the channel, the
source or destination peripheral needs to terminate a block transfer. In this mode, the peripheral is the flow
controller.
Flow control mode (DMAC_CFGx.FCMODE): Special mode that only applies when the destination peripheral is
the flow controller. It controls the pre-fetching of data from the source peripheral.
Transfer hierarchy: Figure 24-2 on page 263 illustrates the hierarchy between DMAC transfers, block transfers,
transactions (single or burst), and AMBA transfers (single or burst) for non-memory peripherals. Figure 24-3 on
page 263 shows the transfer hierarchy for memory.