Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
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7.1.1.2 Internal 16 Kbyte Fast SRAM
The SAM9263 integrates a 16 Kbyte SRAM, mapped at address 0x0050 0000. This SRAM is single cycle
accessible at full Bus Matrix speed.
7.1.2 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be
changed with two parameters. After reset, the ROM is mapped at both addresses 0x0000_0000 and
0x0040_0000.
REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once the system has
booted. Refer to Section 19. “SAM9263 Bus Matrix” for more details.
When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is
done via hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 7-1 on page 24.
The SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal
memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus
Interface.
7.1.2.1 BMS = 1, Boot on Embedded ROM
The system boots on Boot Program.
 Boot at slow clock
 Auto baudrate detection
 Downloads and runs an application from external storage media into internal SRAM
 Downloaded code size depends on embedded SRAM size
 Automatic detection of valid application
 Bootloader on a non-volatile memory
 SD Card
 NAND Flash
 SPI DataFlash and Serial Flash connected on NPCS0 of the SPI0
 Interface with SAM-BA
®
Graphic User Interface to enable code loading via:
 Serial communication on a DBGU
 USB Bulk Device Port
7.1.2.2 BMS = 0, Boot on External Memory
 Boot at slow clock
 Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus,
Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI0 CS0 (BMS = 0) the user must:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and Start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock.
4. Switch the main clock to the new value.