Datasheet

251
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
23.3 Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for
redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of
words in the main area plus the number of words in the extra area used for redundancy.
The only configuration required for ECC is the NAND Flash or the SmartMedia page size (528/1056/2112/4224).
Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR).
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the
SmartMedia is detected. Read and write access must start at a page boundary.
ECC results are available as soon as the counter reaches the end of the main area. Values in the ECC Parity
Register (ECC_PR) and ECC NParity Register (ECC_NPR) are then valid and locked until a new start condition
occurs (read/write command followed by address cycles).
23.3.1 Write Access
Once the flash memory page is written, the computed ECC code is available in the ECC Parity Error (ECC_PR)
and ECC_NParity Error (ECC_NPR) registers. The ECC code value must be written by the software application in
the extra area used for redundancy.
23.3.2 Read Access
After reading the whole data in the main area, the application must perform read accesses to the extra area where
ECC code has been previously stored. Error detection is automatically performed by the ECC controller. Please
note that it is mandatory to read consecutively the entire main area and the locations where Parity and NParity
values have been previously stored to let the ECC controller perform error detection.
The application can check the ECC Status Register (ECC_SR) for any detected errors.
It is up to the application to correct any detected error. ECC computation can detect four different circumstances:
 No error: XOR between the ECC computation and the ECC code stored at the end of the NAND Flash or
SmartMedia page is equal to 0. No error flags in the ECC Status Register (ECC_SR).
 Recoverable error: Only the RECERR flag in the ECC Status register (ECC_SR) is set. The corrupted word
offset in the read page is defined by the WORDADDR field in the ECC Parity Register (ECC_PR). The
corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity Register
(ECC_PR).
 ECC error: The ECCERR flag in the ECC Status Register is set. An error has been detected in the ECC
code stored in the Flash memory. The position of the corrupted bit can be found by the application
performing an XOR between the Parity and the NParity contained in the ECC code stored in the flash
memory.
 Non correctable error: The MULERR flag in the ECC Status Register is set. Several unrecoverable errors
have been detected in the flash memory page.
ECC Status Register, ECC Parity Register and ECC NParity Register are cleared when a read/write command is
detected or a software reset is performed.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) hsiao code is used. 32-bit ECC is
generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words. Of the 32 ECC bits, 26
bits are for line parity and 6 bits are for column parity. They are generated according to the schemes shown in
Figure 23-2 and Figure 23-3.