Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
244
22.6.4 SDRAMC Low Power Register
Name: SDRAMC_LPR
Address: 0xFFFFE210 (0), 0xFFFFE810 (1)
Access: Read/Write
• LPCB: Low-power Configuration Bits
• PASR: Partial Array Self-refresh (only for low-power SDRAM)
PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks
of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set
according to the SDRAM device specification.
• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode
depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
• DS: Drive Strength (only for low-power SDRAM)
DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-
ter must be set according to the SDRAM device specification.
• TIMEOUT: Time to define when low-power mode is enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–– TIMEOUT DS TCSR
76543210
– PASR – – LPCB
Value Description
00
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM
device.
01
The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated and the
SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access.
10
The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to
low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access.
11
The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power
SDRAM.
Value Description
00 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
01 The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
10 The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
11 Reserved.