Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
242
22.6.3 SDRAMC Configuration Register
Name: SDRAMC_CR
Address: 0xFFFFE208 (0), 0xFFFFE808 (1)
Access: Read/Write
• NC: Number of Column Bits
Reset value is 8 column bits.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NB: Number of Banks
Reset value is two banks.
• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles are managed.
31 30 29 28 27 26 25 24
TXSR TRAS
23 22 21 20 19 18 17 16
TRCD TRP
15 14 13 12 11 10 9 8
TRC TWR
76543210
DBW CAS NB NR NC
Value Column Bits
00 8
01 9
10 10
11 11
Value Row Bits
00 11
01 12
10 13
11 Reserved
Value Number of Banks
02
14
Value CAS Latency (Cycles)
00 Reserved
01 1
10 2
11 3