Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
234
22.5.3 Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM
controller generates a precharge command, activates the new row and initiates a read or write command. To
comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (t
RP
)
command and the active/read (t
RCD
) command. This is described in Figure 22-4 below.
Figure 22-4. Read Burst with Boundary Row Access
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
T
RP
= 3
SDWE
Row m
col a
col a col b col c col d col e
Dna Dnb
Dnc
Dnd
T
RCD
= 3 CAS = 2
col b
col c
col d
Dma Dmb
Dmc
Dmd
Row n
Dme