Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
216
21.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at
high clock rate, with the set of slow clock mode parameters. See Figure 21-32. The external device may not be fast
enough to support such timings.
Figure 21-33 illustrates the recommended procedure to properly switch from one mode to the other.
Figure 21-32. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
A
[25:2]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
111 2
3
2
NWE_CYCLE = 7
NORMAL MODE WRITE
Slow clock mode transition is detected:
Reload Configuration Wait State
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
SLOW CLOCK MODE WRITE
NBS0, NBS1,
NBS2, NBS3,
A0,A1