Datasheet

21
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
 SPI0 Transmit Channel
 SSC1 Transmit Channel
 SSC0 Transmit Channel
 DBGU Receive Channel
 USART2 Receive Channel
 USART1 Receive Channel
 USART0 Receive Channel
 AC97C Receive Channel
 SPI1 Receive Channel
 SPI0 Receive Channel
 SSC1 Receive Channel
 SSC0 Receive Channel
 MCI1 Transmit/Receive Channel
 MCI0 Transmit/Receive Channel
6.4 DMA Controller
 Acts as one Matrix Master
 Embeds 2 unidirectional channels with programmable priority
 Address Generation
 Source/destination address programming
 Address increment, decrement or no change
 DMA chaining support for multiple non-contiguous data blocks through use of linked lists
 Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a
stream of data into non-contiguous fields in system memory.
 Gather support for extracting fields from a system memory area into a contiguous transfer
 User enabled auto-reloading of source, destination and control registers from initially programmed
values at the end of a block transfer
 Auto-loading of source, destination and control registers from system memory at end of block transfer
in block chaining mode
 Unaligned system address to data transfer width supported in hardware
 Channel Buffering
 Two 8-word FIFOs
 Automatic packing/unpacking of data to fit FIFO width
 Channel Control
 Programmable multiple transaction size for each channel
 Support for cleanly disabling a channel without data loss
 Suspend DMA operation
 Programmable DMA lock transfer support.
 Transfer Initiation
 Supports four external DMA Requests
 Support for software handshaking interface. Memory mapped registers can be used to control the flow
of a DMA transfer in place of a hardware handshaking interface
 Interrupt
 Programmable interrupt generation on DMA transfer completion, Block transfer completion,
Single/Multiple transaction completion or Error condition