Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
208
21.10.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float
period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data
float period, no additional tdf wait states will be inserted.
Figure 21-23, Figure 21-24 and Figure 21-25 illustrate the cases:
 read access followed by a read access on another chip select,
 read access followed by a write access on another chip select,
 read access followed by a write access on the same chip select,
with no TDF optimization.
Figure 21-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects
TDF_CYCLES = 6
TDF_CYCLES = 6
TDF_MODE = 0
(optimization disabled)
A[
25:2]
read1 cycle
Chip Select Wait State
MCK
read1 controlling signal
(NRD)
read2 controlling signal
(NRD)
D[31:0]
read1 hold = 1
read 2 cycle
read2 setup = 1
5 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1