Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
202
21.9 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention
or operation conflict.
21.9.1 Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that
there is no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD
lines are all set to 1.
Figure 21-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
Figure 21-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS0
NRD_CYCLE
Chip Select
Wait State
NWE_CYCLE
MCK
NCS2
NRD
NWE
D[31:0]
Read to Write
Wait State