Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
20
6.2.3 Master to Slave Access
In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example,
allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not
wired, and are shown as “–” in Table 6-3.
6.3 Peripheral DMA Controller
 Acts as one Matrix Master
 Allows data transfers between a peripheral and memory without any intervention of the processor
 Next Pointer support, removes heavy real-time constraints on buffer management.
 Twenty channels
 Two for each USART
 Two for the Debug Unit
 Two for each Serial Synchronous Controller
 Two for each Serial Peripheral Interface
 Two for the AC97C Controller
 One for each Multimedia Card Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (low
to high priorities):
 DBGU Transmit Channel
 USART2 Transmit Channel
 USART1 Transmit Channel
 USART0 Transmit Channel
 AC97C Transmit Channel
 SPI1 Transmit Channel
Table 6-3. Masters to Slaves Access
Master 0 1234567&8
Slave
OHCI USB
Host
Controller
Image
Sensor
Interface
Two D
Graphics
Controller
DMA
Controller
Ethernet
MAC
LCD
Controller
Peripheral
DMA
Controller
ARM926
Data &
Instruction
0Internal ROMX XXXXXX X
1
Internal 80 Kbyte
SRAM
X XXXXXX X
2
Internal 16 Kbyte
SRAM Bank
X XXXXXX X
3
LCD Controller
User Interface
– –––––– X
DMA Controller
User Interface
– –––––– X
USB Host User
Interface
– –––––– X
4
External Bus
Interface 0
X XXXXXX X
5
External Bus
Interface 1
X XXXXXX X
6 Peripheral Bridge - - - X - - X X