Datasheet

199
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
21.8.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in
case of consecutive write cycles in the same memory (see Figure 21-13). However, for devices that perform write
operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 21-13. Null Setup and Hold Values of NCS and NWE in Write Cycle
21.8.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
21.8.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation.
NCS
MCK
NWE,
NWR0, NWR1,
NWR2, NWR3
D[31:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1