Datasheet

19
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
 One Address Decoder provided per Master
 Three different slaves may be assigned to each decoded memory area: one for internal boot, one for
external boot, one after remap
 Boot Mode Select
 Non-volatile Boot Memory can be internal or external
 Selection is made by BMS pin sampled at reset
 Remap Command
 Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
 Allows Handling of Dynamic Exception Vectors
6.2.1 Matrix Masters
The Bus Matrix of the SAM9263 manages nine masters, thus each master can perform an access concurrently
with others to an available slave peripheral or memory.
Each master has its own decoder, which is defined specifically for each master.
6.2.2 Matrix Slaves
The Bus Matrix of the SAM9263 manages eight slaves. Each slave has its own arbiter, thus allowing to program a
different arbitration per slave.
The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a
slave on the Matrix. They share the same layer, as programming them does not require a high bandwidth.
Table 6-1. List of Bus Matrix Masters
Master 0 OHCI USB Host Controller
Master 1 Image Sensor Interface
Master 2 Two D Graphic Controller
Master 3 DMA Controller
Master 4 Ethernet MAC
Master 5 LCD Controller
Master 6 Peripheral DMA Controller
Master 7 ARM926 Data
Master 8 ARM926 Instruction
Table 6-2. List of Bus Matrix Slaves
Slave 0 Internal ROM
Slave 1 Internal 80 Kbyte SRAM
Slave 2 Internal 16 Kbyte SRAM
Slave 3
LCD Controller User Interface
DMA Controller User Interface
USB Host User Interface
Slave 4 External Bus Interface 0
Slave 5 External Bus Interface 1
Slave 6 Peripheral Bridge