Datasheet

177
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
20.5.7 NAND Flash Support
External Bus Interfaces 0 and 1 integrate circuitry that interfaces to NAND Flash devices.
20.5.7.1 External Bus Interface 0
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI0_CS3A bit in the EBI0 Chip Select Assignment Register to the appropriate value enables the NAND Flash
logic. For details on this register, refer to Section 19.6 “Chip Configuration User Interface”. Access to an external
NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000
and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address
fails to lie in the NCS3 address space. See Figure 20-7 for more information. For details on these waveforms, refer
to Section 21. “Static Memory Controller (SMC)”.
Figure 20-7. NAND Flash Signal Multiplexing on EBI Pins
20.5.7.2 External Bus Interface 1
The NAND Flash logic is driven by the Static Memory Controller on the NCS2 address space. Programming the
EBI1_CS2A bit in the EBI1 Chip Select Assignment Register to the appropriate value enables the NAND Flash
logic. For details on this register, refer to Section 19.6 “Chip Configuration User Interface”. Access to an external
NAND Flash device is then made by accessing the address space reserved to NCS2 (i.e., between 0x9000 0000
and 0x9FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCS2 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address
fails to lie in the NCS2 address space. See Figure 20-7 for more information. For details on these waveforms, refer
to Section 21. “Static Memory Controller (SMC)”.
SMC
NRD
NWR0_NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx
NANDWE
NANDOE