Datasheet

173
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
20.5.6.2 CFCE1 and CFCE2 Signals
To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd
byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the
corresponding NCS pin (NCS4 or NCS5). The DBW field in the SMC Mode Register corresponding to the NCS4
and/or NCS5 address space must be set as shown in Table 20-7 to enable the required access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select
mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these
waveforms and timings, refer to Section 21. “Static Memory Controller (SMC)”.
Table 20-7. CFCE1 and CFCE2 Truth Table
Mode CFCE2 CFCE1 DBW Comment SMC Access Mode
Attribute Memory NBS1 NBS0 16 bits Access to Even Byte on D[7:0] Byte Select
Common Memory
NBS1 NBS0 16bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
1 0 8 bits Access to Odd Byte on D[7:0]
I/O Mode
NBS1 NBS0 16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
1 0 8 bits Access to Odd Byte on D[7:0]
True IDE Mode
Task File 1 0 8 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Data Register 1 0 16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
Alternate True IDE Mode
Control Register
Alternate Status Read
0 1 Don’t Care Access to Even Byte on D[7:0] Don’t Care
Drive Address 0 1 8 bits Access to Odd Byte on D[7:0]
Standby Mode or Address Space is not
assigned to CF
11 – – –