Datasheet

171
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
20.4 Product Dependencies
20.4.1 I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O
lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO
Controller.
20.5 Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses
and is composed of the following elements:
 the Static Memory Controller (SMC)
 the SDRAM Controller (SDRAMC)
 the ECC Controller (ECC)
 a chip select assignment feature that assigns an AHB address space to the external devices
 a multiplex controller circuit that shares the pins between the different Memory Controllers
 programmable CompactFlash support logic (EBI0 only)
 programmable NAND Flash support logic
20.5.1 Bus Multiplexing
The EBI0 and EBI1 offers a complete set of control signals that share the 32-bit data lines, the address lines of up
to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines
at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float
times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently
by the SDRAM Controller without delaying the other external Memory Controller accesses.
20.5.2 Pull-up Control
The chip select assignment registers EBI0_CSA and EBI1_CSA in the Chip Configuration User Interface permit
enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up
resistors are enabled after reset. Setting the corresponding EBIx_CSA.EBIx_DBPUC bit disables the pull-up
resistors on the lines D0–D15. Enabling the pull-up resistor on the lines D16–D31 can be performed by
programming the appropriate PIO controller.
20.5.3 Static Memory Controller
For information on the Static Memory Controller, refer to Section 21. “Static Memory Controller (SMC)”.
20.5.4 SDRAM Controller
For information on the SDRAM Controller, refer to Section 22. “SDRAM Controller (SDRAMC)”.
20.5.5 ECC Controller
For information on the ECC Controller, refer to Section 23. “Error Correction Code Controller (ECC)”.