Datasheet

167
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Notes: 1. x indicates 0 or 1
2. Only for EBI0
20.3.1 Hardware Interface
Table 20-4 details the connections to be applied between the EBI pins and the external devices for each Memory
Controller.
Table 20-3. EBIx Pins and Memory Controllers I/O Lines Connections
EBIx Pins
(1)
SDRAMC I/O Lines SMC I/O Lines
EBIx_NWR1/NBS1/CFIOR NBS1 NWR1/NUB
EBIx_A0/NBS0 Not Supported SMC_A0/NLB
EBIx_A1/NBS2/NWR2 Not Supported SMC_A1
EBIx_A[11:2] SDRAMC_A[9:0] SMC_A[11:2]
EBIx_SDA10 SDRAMC_A10 Not Supported
EBIx_A12 Not Supported SMC_A12
EBIx_A[14:13] SDRAMC_A[12:11] SMC_A[14:13]
EBIx_A[22:15] Not Supported SMC_A[22:15]
EBIx_A[25:23]
(2)
Not Supported SMC_A[25:23]
EBIx_D[31:0] D[31:0] D[31:0]
Table 20-4. EBI Pins and External Static Devices Connections
Signals:
EBI0_, EBI1_
Pins of the SMC Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
4 x 8-bit
Static
Devices
2 x 16-bit
Static
Devices
32-bit Static
Device
D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7
D8–D15 – D8–D15 D8–D15 D8–D15 D8–15 D8–15
D16–D23 – – – D16–D23 D16–D23 D16–D23
D24–D31 – – – D24–D31 D24–D31 D24–D31
A0/NBS0 A0 – NLB – NLB
(3)
BE0
(6)
A1/NWR2/NBS2 A1 A0 A0 WE
(2)
NLB
(4)
BE2
(6)
A2–A22 A[2:22] A[1:21] A[1:21] A[0:20] A[0:20] A[0:20]
A23–A25
(5)
A[23:25] A[22:24] A[22:24] A[21:23] A[21:23] A[21:23]
NCS0 CS CS CS CS CS CS
NCS1/SDCSCSCSCSCSCSCS
NCS2
(5)
CS CS CS CS CS CS
NCS2/NANDCS
(7)
CS CS CS CS CS CS
NCS3/NANDCS
(5)
CS CS CS CS CS CS
NCS4/CFCS0
(5)
CS CS CS CS CS CS
NCS5/CFCS1
(5)
CS CS CS CS CS CS
NRD/CFOE OE OE OE OE OE OE
NWR0/NWE WE WE
(1)
WE WE
(2)
WE WE
NWR1/NBS1 – WE
(1)
NUB WE
(2)
NUB
(3)
BE1
(6)