Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
166
The connection of some signals through the MUX logic is not direct and depends on the memory controller in use
at the moment.
Table 20-3 on page 167 details the connections between the two memory controllers and the EBI pins.
Table 20-2. EBI1 I/O Lines Description
Name Function Type Active Level
EBI
EBI1_D0–EBI1_D31 Data Bus I/O
EBI1_A0–EBI1_A22 Address Bus Output
EBI1_NWAIT External Wait Signal Input Low
SMC
EBI1_NCS0–EBI1_NCS2 Chip Select Lines Output Low
EBI1_NWR0–EBI1_NWR3 Write Signals Output Low
EBI1_NRD Read Signal Output Low
EBI1_NWE Write Enable Output Low
EBI1_NBS0–EBI1_NBS3 Byte Mask Signals Output Low
EBI for NAND Flash Support
EBI1_NANDCS NAND Flash Chip Select Line Output Low
EBI1_NANDOE NAND Flash Output Enable Output Low
EBI1_NANDWE NAND Flash Write Enable Output Low
SDRAM Controller
EBI1_SDCK SDRAM Clock Output
EBI1_SDCKE SDRAM Clock Enable Output High
EBI1_SDCS SDRAM Controller Chip Select Line Output Low
EBI1_BA0–EBI1_BA1 Bank Select Output
EBI1_SDWE SDRAM Write Enable Output Low
EBI1_RAS - EBI1_CAS Row and Column Signal Output Low
EBI1_NWR0–EBI1_NWR3 Write Signals Output Low
EBI1_NBS0–EBI1_NBS3 Byte Mask Signals Output Low
EBI1_SDA10 SDRAM Address 10 Line Output