Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
164
20.2.2 External Bus Interface 1
Figure 20-2 shows the organization of the External Bus Interface 1.
Figure 20-2. Organization of the External Bus Interface 1
External Bus Interface 1
D[15:0]
A[15:2], A[20:18]
PIO
MUX
Logic
NAND Flash
Logic
User Interface
Chip Select
Assignor
Static
Memory
Controller
SDRAM
Controller
Bus Matrix
APB
AHB
Address Decoders
A16/BA0
A0/NBS0
A1/NWR2/NBS2
A17/BA1
NCS0
NRD
NCS1/SDCS
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDCK
SDCKE
RAS
CAS
SDWE
D[31:16]
NCS2/NANDCS
NWAIT
SDA10
NANDOE
NANDWE
ECC
Controller
A21/NANDALE
A22/NANDCLE