Datasheet

15
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
4.2.1 Power-up Sequence
For the first power-up, VDDCORE is to be established before VDDBU. VDDBU powers the Backup power switch;
it must always be powered to ensure correct behavior.
VDDCORE and VDDBU are controlled by internal POR (Power-on Reset) to guarantee that these power sources
reach their target values prior to the release of POR.
 VDDIOM0, VDDIOM1, VDDIOP0, VDDIOP1 and VDDIOP2 must NOT be powered until VDDCORE has
reached a level superior to V
T+
.
 VDDIOP0 must be ≥ VIH (refer to Table 46-2 “DC Characteristics” for more details) within (t
RST
+ T1) after
VDDCORE reached V
T+
.
 VDDIOM0 and VDDIOPM1 must reach VOH (refer to Table 46-2 “DC Characteristics” for more details)
within (t
RST
+ T1 + T2) after VDDCORE has reached V
T+
 t
RST
is a POR characteristic
 T1 = 3 x t
SLCK
 T2 = 1 6 x t
SLCK
As t
SLCK
is the period of the external 32.768 kHz oscillator.
 t
RST
= 80 µs
 T1 = 91.5 µs
 T2 = 488 µs
Figure 4-1. VDDCORE and VDDIO Constraints at Startup
VDD (V)
Core Supply POR output
VDDIOtyp
V
T+
t
SLCK
VDDCORE
VDDIO
VDDCOREtyp
Voh
VDDIO > V
OH
BMS sampling level
T2
t
RST
T1