Datasheet

149
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
19. SAM9263 Bus Matrix
19.1 Description
Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between
multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 9
AHB Masters to
7 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the
default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration
User Interface with registers that allow the Bus Matrix to support application specific features.
19.2 Memory Mapping
Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several
memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash,
etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that allows to perform
remap action for every master independently.
19.3 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
some masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus
granting mechanism allows to set a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters: no default master, last access
master and fixed default master.
19.3.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No
Default Master, suits low power mode.
19.3.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to the last master that
performed an access request.
19.3.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike last access master, the fixed master doesn’t change unless the user modifies it by a software action (field
FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave
Configuration Registers, one for each slave, that allow to set a default master for each slave. The Slave
Configuration Register contains two fields:
DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master
type (no default, last access master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field allows to
choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the
Bus Matrix user interface description.