Datasheet

SAM9263 [DATASHEET]

Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16

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14.4 Functional Description

The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided

by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode

Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow

Clock is 32.768 kHz). The 32-bit counter can count up to 2

seconds, corresponding to more than 136 years, then

roll over to 0.

The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is

achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status

events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to

trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several

executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the

status register is clear.

The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As

this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the

same value to improve accuracy of the returned value.

The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm

maximum value, corresponding to 0xFFFF_FFFF, after a reset.

The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to

start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow

Clock equal to 32.768 kHz.

Reading the RTT_SR status register resets the RTTINC and ALMS fields.

Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed

value. This also resets the 32-bit counter.

Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):

1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles

after the write of the RTTRST bit in the RTT_MR.

2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status