Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1086
USART: In Section 33.5.1 “I/O Lines” on page 515 added information on TXD enabled.
In Section 33.6.2 “Receiver and Transmitter Control” on page 521, corrected information on software
reset.
4825
4367
CAN: In Figure 36-7 on page 642 corrected mode switch conditions. 4089
UDP: Table 42-2 on page 856, “Supported Endpoint” column updated in the USB Communication Flow.
Updated description of bit EPEDS in the USB_CSR register on page 885 for details on control endpoints
not affected.
Updated: write 1=.....”RX_DATA_BK0: Receive Data Bank 0”bitfield in USB_CSR
Updated: write 0 =...”TXPKTRDY: Transmit Packet Ready” bitfield in USB_CSR
3476
4063
4099
LCDC: In Table 43-1, “I/O Lines Description,” on page 890, updated description of LCDDEN.
Updated Table 43-4, ”Little Endian Memory Organization”, on page 894, with Pixel 24 bpp unpacked
format.
Updated bit description ”PIXELSIZE: Bits per pixel” on page 924 in LCDCON2 register, updated bit
configuration table with new value for 24 bpp unpacked.
In Section 43.11.24 “Power Control Register” on page 938, LCD_PWR bit description, changed all
occurrences of “pin” to “signal”.
3587
ISI: Added information to CODEC_ON bit description in Section 45.4.1 “ISI Control 1 Register” on page
1005.
Added Bit 3 CDC_PND to Section 45.4.3 “ISI Status Register” on page 1009.
Correction to name of Section 45.4.8 “ISI Preview Decimation Factor Register” on page 1016.
Added note on ISI_PCK to Table 45-9, “Register Mapping,” on page 1004.
Updated ISI_RST bit description in Section 45.4.1 “ISI Control 1 Register” on page 1005.
3518
3519
3250
3524
In Table 46-3, “Power Consumption for Different Modes,” on page 1026, added note for SRAM access. 3904
Added Table 46-7, “Master Clock Waveform Parameters,” on page 1029. 4304
Updated Section 46.6 “Crystal Oscillator Characteristics” on page 1029.
4092,
3862
Corrected VDDOSC value in Table 46-9, “32 kHz Oscillator Characteristics,” on page 1029. 4244
Errata changes: Inserted “Two D Graphic Controller (TDGC)” , Section 50.1.2.1 “Polygon Fill Function”
on page 1017.
Inserted “EMACB” , Section 50.1.8.1 “Transmit Underrun Errors” on page 1019.
Updated “USART” , Section 49.2.19.3 “CTS Signal in Hardware Handshake” on page 1038
.
Inserted “U
SART” , Section 50.1.21.1 “SCK1 and SCK2 are Inverted” on page 1027.
Inserted “SDRAM Controller” , Section 50.1.13.3 “JEDEC Standard Compatibility” on page 1022.
Inserted Section 50.1.11.1 “NTRST: Device does not boot correctly due to power-up sequencing issue”
on page 1021.
Inserted Section 50.1.4.1 “BMS Does Not Have Correct State” on page 1017.
4093
4093
4093
4465
4221
3882
Revision
6249C Comments
Change
Request
Ref.