Datasheet

1085
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Revision
6249C Comments
Change
Request
Ref.
In Section 4.1 “324-ball TFBGA Package Outline” on page 10 corrected package top view. 4463
All new information for Table 7-1, “List of Bus Matrix Masters,” on page 16, Table 7-2, “List of Bus Matrix
Slaves,” on page 17 and Table 7-3, “Masters to Slaves Access,” on page 18.
4466
In Section 9.3 “Shutdown Controller” on page 29, corrected reference to shutdown pin. 3870
In Section 5.2 “Power Consumption” on page 13, specified static current consumption as worst case.
Corrected Section 10.4.7 “NAND Flash” on page 41, with information on EMAC.
3825
In Section 10.4.3 “EBI1” on page 41, added Ethernet 10/100 MAC to the System Resource Multiplexing
list of EBI1.
4064
In Section 10.4.11 “Image Sensor Interface” on page 42 and Section 10.4.12 “Timers” on page 42,
removed mention of keyboard interfaces.
4407
In Table 11-3 “SAM9263 JTAG Boundary Scan Register” on page 87, changed pin 246 to NC.
Boot: Updated supported crystals in Table 12-1, “Crystals Supported by Software Auto-detection (MHz),”
on page 98.
Corrected Figure 12-3, “LDR Opcode,” on page 99.
Updated supported DataFlash device references in Table 12-2, “DataFlash Devices,” on page 100.
4230
4450
4186
EBI: Updated Figure 20-1, “Organization of the External Bus Interface 0,” on page 163 and Figure 20-2,
“Organization of the External Bus Interface 1,” on page 164 and Table 20-5, “EBI Pins and External
Devices Connections,” on page 168 with NANDALE and NANDCLE pins. Removed note on CLE and
ALE NAND Flash signals. Removed reference to EBI0 for NANDOE and NANDWE.
In Table 20-2, “EBI1 I/O Lines Description,” on page 166, corrected EBI address bus width.
In Table 20-5, “EBI Pins and External Devices Connections,” on page 168, corrected NAND Flash AD to
I/O. Added Note
(5)
on CE and NAND Flash.
4149
3850
3905
SHDW: In Table 17-2, “Register Mapping,” on page 143, corrected offset value for SHDW_SR register. 4224
SMC: In Section 21.7.2.1 “Byte Write Access” on page 192, added information that boot is not allowed in
Byte Write Access mode.
3252
ECC: Section 23.3 “Functional Description” on page 251 updated.
Section 23.3.1 “Write Access” on page 251 and Section 23.3.2 “Read Access” on page 251 updated.
Section 23.4.4 “ECC Parity Register” on page 259 and Section 23.4.5 “ECC NParity Register” on page
260 updated.
In Table 23-1, “Register Mapping,” on page 255, corrected offset value for ECC_SR.
3970
4306
PMC: In Section 27.3 “Processor Clock Controller” on page 339, new details on PCK disable. 3835
PIO: Notes
(1)
,
(2)
and
(3)
updated in Table 31-2, “Register Mapping,” on page 411. 3974
SPI: In Section 31.6.4 “SPI Slave Mode” on page 473, updated information on OVRES
bit. 3943
TWI: New Section 33. “Two-wire Interface (TWI)” on page 481.