Datasheet

1081
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
SDRAMC:
Section 22.6.1 “SDRAMC Mode Register”; changed MODE bit description.
SDRAMC Configuration Register “CAS: CAS Latency” on page 242, changed CAS bit description
4593
4623
SHDWC:
Table 17-1 “Shutdown Controller Block Diagram”; corrected register names in the block diagram. 4734
SMC:
Section 22.14 ”Programmable IO Delays”, added to datasheet
Section 21.8.5 “Coding Timing Parameters”, “Effective Value” column under “Permitted Range” updated in
Table 21-4 on page 201.
Section 21.9.3.1 “User Procedure”, Instructions regarding configuration parameters of SMC Chip Select
added.
rfo/4951
5604
5621
SPI:
Section 31.7.9 “SPI Chip Select Register”, note pertaining to BITS field added. This note is referenced in the
BITS bitfield description and Section 31.6.4 “SPI Slave Mode”
5588
SSC:
Section 34.8.3 “SSC Receive Clock Mode Register”, corrected bit name to STTDLY. 4778
TC:
Section 38.7 “Timer Counter (TC) User Interface”, Register mapping consolidated into one table, offsets of
channel registers indexed and referenced in the register tables that follow. Functional value of WAVE is
given.
Section 38.7.2 “TC Block Mode Register”, typo fixed in bit fields 2 and 3.
Section 38.7.4 “TC Channel Mode Register: Capture Mode”, bit field 15 updated.
4583
TDGC:
All mention of Polygon Fill feature removed. Fill Control Register, Vertex X, Vertex Y registers removed from
User Interface, addresses reassigned as “Reserved” in, Table 44-2, “TDGC Register Mapping,” on
page 962.
User Interface: 2D Graphics Controller (2DGC) replaced by Two D Graphics Controller (TDGC).
Section 44.5.23 “VRAM Size Register”, VSIZE field (updated with explicit hex radix).
Section 44.5.4 “Source/Begin Y Register”, typo “YCOR” fixed, = “YSRC”.
Section 44.5.15 “Extended End Y Register”, typo EXT_BY fixed, = “EXT_EY”.
Table title number removed from tables in bitfield descriptions.
5205
5627
rfo
TWI:
Section 33. ”Two-wire Interface (TWI)”, the implementation of the TWI has been updated in this product.
rfo
UDP:
Section 42.6.10 “UDP Endpoint Control and Status Register”, update to code and added instructions
regarding USB clock and system clock rate.
4462
Updated note under code with text“....a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is
required...” Ditto for RX_DATA and TXPKTRDY bit fields
4487
Section 42.2 “Block Diagram”, in 2nd paragraph under the block diagram, peripheral clock requirements
updated.
4508
Revision
6249E Comments (Continued)
Change
Request
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