Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1080
DMAC:
Figure 24-4, “External DMA Request Timing,” on page 266, updated.
Section “External DMA Request Definition”, 3rd paragraph CTLxL.xxx typos fixed. “The DMA ends...” added
to 4th paragraph.
Multiple bits represented by “x” in Bit names from Section 24.4.11 on page 305 to Section 24.4.23 on page
317
Section 24.4.7 “Configuration Register for Channel x High”, SRC_PER bitfield description unscrambled from
previous paragraph.
Section 24.4 “DMA Controller (DMAC) User Interface”, DMA_IdReg, DMAC_DmaTestReg removed.
address 0x3a4, 0x3b8 is reserved.
5503
rfo
5504
5524
5644
Debug and Test
Figure 11-6, “AMP Mictor Connector Orientation”, replaced internal product reference in figure.
Table 11-3 “SAM9263 JTAG Boundary Scan Register”, pin names assigned to bits 517, 205. pin name
updated for bit 203.
5385
5607
EMAC:
Section 41.3.1 ”Clock” added to Functional Description 3328
GPBR:
The General Purpose Backup Registers section has been added.
rfo
ISI:
Section 45.4.7 “ISI Preview Register”: PREV_HSIZE and PREV_VSIZE updated with RGB only comments. 5430
LCDC:
Section 43.10.2 “TFT Mode Example”, “HFP....” line, typo corrected: “HPW = (64-2)” 5619
MCI:
Section 40.1 ”Overview”, MCI supports Multimedia Card (MMC) Specification V3.31 5282
PMC and CKGR:
Section 27.1 “Overview”: “PCK must be switched off........”
Section 27.3 “Processor Clock Controller”, new information added explaining Idle Mode.
4322
Figure 26-1, “Typical Slow Clock Crystal Oscillator Connection”, corrected GNDPLL to GNDBU 4470
Section 26.4.2 “Divider and Phase Lock Loop Programming”, added the last line, specific to PLLA and PLLB
initialization.
Section 27.7 “Programming Sequence”;
in step 3: “Setting PLLA and divider A”, ICPPLA requirement added to 1st paragraph.
in step 4: “Setting PLLB and divider B”, ICPPLB requirement added to 1st paragraph.
5046
Section 27.7 “Programming Sequence”;
in step 6, “Selection of Master CLock and Processor Clock”, 4th paragraph, this text has been added: “By
default, the PRES parameter is set to 0 which means that master clock is equal to slow clock.”
5596
PWM:
Section 37.6 “Pulse Width Modulation Controller (PWM) User Interface”, Channel-dependent registers are
indexed. (see Table 37-2 on page 696)
Section 37.6.13 “PWM Channel Update Register” Fixed typos in table: CPD (PWM_CMRx Register)
4486
5185
RSTC:
Section 13.3.4.4 “Software Reset”, PERRST must be used with PROCRST, except for debug purposes. 5436
Revision
6249E Comments (Continued)
Change
Request
Ref.