Datasheet
1077
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Revision
6249I Comments
Change
Request
Ref.
Electrical Characteristics:
Table 46-3 “Power Consumption for Different Modes” edited: VDDCORE 1.2V --> 1.3V.
Table 46-6 “Processor Clock Waveform Parameters” and Table 46-7 “Master Clock Waveform Parameters”
edited: VDDCORE 1.2V --> 1.3V ± 2%.
7345
Back page:
Latest back page file used.
rfo
Revision
6249H Comments
Change
Request
Ref.
Erratum “RSTC: Reset during SDRAM Accesses” removed from Rev A
Erratum “SDCLK Clock Active after Reset “removed from Rev B
47.3.2 “Power Sequence” moved to a Section 46.4 on page 1028
RFO
EBI0_NCS3 restriction added to
Section 9.4.2 “ETM™” on page 44 6053
In Section 19. “SAM9263 Bus Matrix”, slave number changed from 7 to 6 in ”Description”, and in ”Bus Matrix
User Interface”.
6055
1st column header of Table 49-1, ”SAM9263 Ordering Information”, on page 1057 edited. 6066
Section 33. “Two-wire Interface (TWI)” on page 453 changed: TWI2_6212E.fm --> TWI_6212C.fm. 6081
Erratum added to rev A as Section 50.2.13.1 “RSTC: Reset during SDRAM Accesses” on page 1065, and to
rev B as Section 50.1.11.2 “RSTC: Reset during SDRAM Accesses” on page 1062
6083
Voltage row added to Table 46-8, ”XIN Clock Electrical Characteristics”, on page 1029. 6165
Rev A and B MCI errata “SDIO interrupt does not work with slots other than A” edited. 6169
Bit values changed in Section 27.9.16 “PMC Interrupt Mask Register” on page 364. 6311
‘All peripheral clocks are deactivated’ added to Section 46.3.1 “Power Consumption versus Modes” on page
1025
6343
Second paragraph in Section 4.3 “Programmable I/O Lines Power Supplies” on page 17 edited.
Section 46.9.4 “SDRAMC Signals” on page 1040 edited, 2 tables inserted.
6395
Table 46-28, ”SDRAMC Clock Signal”, on page 1040 edited. 6396
‘Selectable by software...’ removed from Table 46-2, ”DC Characteristics”, on page 1024. 6402
3 Rev B errata added: USART Section 50.1.21.6 “Bad value in Number of Errors Register” on page 1069,
SSC Section 50.1.15.3 “Unexpected Delay on TD output” on page 1066, and PWM Section 50.1.16.1 “Zero
Period” on page 1066.
6466
Rev A USART errata Section 50.1.21.4 on page 1027 to Section 50.1.21.6 on page 1028 duplicated to Rev B. 6475