Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1076
Revision
6249J Comments
Change
Request
Ref.
Overview:
Section 5.3 “Reset Pins”, removed line “The NRST signal is inserted in the Boundary Scan.” 6783
CAN:
Figure 36-7, TEC and REC parameters to pass from and to “ERROR ACTIVE” to “ERROR PASSIVE”
interchanged.
7511
Electrical Characteristics:
Table 46.11.1 “SPI”, simplified figure titles. The new titles are as follows:
Table 46.11.1.1 “Maximum SPI Frequency”
Table 46-11 “SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)”
Table 46-12 “SPI Slave Mode 0 and 3”
Table 46-13 “SPI Slave Mode 1 and 2”
Section 46.11.2 “ISI”, updated whole ISI section with the one from SAM9260 DS (Doc. version J)
Section 46.9.4 “SDRAMC Signals”, updated timing for EBI0 and EBI1 at 120MHz/3.3V
6872
6641
rfo
Errata:
Section 50.1.15.1 “SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on”
and Section 50.2.14.1 “SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-
on” sections added.
6069
Section 50.1.12 “Reset Controller (RSTC)”
Section 50.1.12.1 “RSTC: Reset During SDRAM Accesses” , added to Rev A parts errata.
Section 50.1.11 “Reset Controller (RSTC)”
Section 50.1.11.2 “RSTC: Reset during SDRAM Accesses”, added to Rev B parts errata.
6086
Section 50.1.21 “USART” and Section 50.2.23 “USART”, text updated in:
Section 50.1.21.1 “RXBRK Flag Error in Asynchronous Mode”
Section 50.2.23.1 “RXBRK Flag Error in Asynchronous Mode”
6629
MATRIX:
Section 19.6.1 “Bus Matrix TCM Configuration Register”, register name, reset value and bit fields updated 6650
PMC:
Section 27.3 “Processor Clock Controller”, text updated 7392
SMC:
Table 21.8.6 “Reset Values of Timing Parameters” , former Table 20-5. “Reset Values of Timing
Parameters”
removed and added cross reference to Table 21-8 “Register Mapping”.
6742
TWI:
Removed Multi-Master Mode and Slave mode references. 7422