Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1072
28-Jan-16
Section 16. “Watchdog Timer (WDT)”
Added Section 16.2 “Embedded Characteristics”
Section 17. “Shutdown Controller (SHDWC)”
Added Section 17.2 “Embedded Characteristics”
Section 19. “SAM9263 Bus Matrix”
Table 19-1 “Register Mapping”: removed reset value from write-only registers
Removed reset value from Section 19.5.5 “Bus Matrix Master Remap Control Register” (reset value is provided in Table
19-1 “Register Mapping”)
Removed reset value from Section 19.6.1 “Bus Matrix TCM Configuration Register”, Section 19.6.2 “EBI0 Chip Select
Assignment Register” and Section 19.6.3 “EBI1 Chip Select Assignment Register” (reset values are provided in Table
19-2 “Register Mapping (Chip Configuration User Interface)”)
Section 20. “External Bus Interface (EBI)”
Section 20.5.6.2 “CFCE1 and CFCE2 Signals”: “The Chip Select Register (DBW field in the corresponding Chip Select
Register) of the NCS4” corrected to “The DBW field in the SMC Mode Register corresponding to the NCS4”
Updated Section 20.6.3.2 “Software Configuration - 8-bit NAND Flash” to add mention of CS2
Section 21. “Static Memory Controller (SMC)”
Updated Section 21.8.1.3 “Read Cycle” and Section 21.8.3.3 “Write Cycle”
Updated Section 21.8.6 “Reset Values of Timing Parameters”
Section 21.13.2 “Byte Access Type in Page Mode”: “SMC_REGISTER” corrected to “SMC Mode Register”
Section 22. “SDRAM Controller (SDRAMC)”
Table 22-8 “Register Mapping”: access “Read” corrected to “Read/Write” for SDRAMC_MDR
Removed reset value from Section 22.6.1 “SDRAMC Mode Register”, Section 22.6.2 “SDRAMC Refresh Timer
Register”, Section 22.6.3 “SDRAMC Configuration Register”, and Section 22.6.4 “SDRAMC Low Power Register” (reset
values are provided in Table 22-8 “Register Mapping”)
Section 23. “Error Correction Code Controller (ECC)”
Table 23-1 “Register Mapping”: removed reset value from ECC_CR (register is write-only)
Section 24. “DMA Controller (DMAC)”
Table 24-3 “Register Mapping”:
- removed reset value from write-only registers
- added reset value 0x0 for DMAC_CTL0L, DMAC_CTL0H, DMAC_CTL1L, and DMAC_CTL1H
Removed reset value from register description sections (reset values are provided in Table 24-3 “Register Mapping”)
Corrected title of Section 24.4.13 “Interrupt Mask Registers” (was “Interrupt Status Registers”)
Section 25. “Peripheral DMA Controller (PDC)”
Table 25-1 “Register Mapping”: removed reset value from PERIPH_PTCR (register is write-only)
Section 27. “Power Management Controller (PMC)”
Table 27-3 “Register Mapping”: access for PMC_PLLICPR changed from “Write-only” to “Read/Write”
Section 27.9.17 “PLL Charge Pump Current Register”: access changed from “Write-only” to “Read/Write”
Section 28. “Advanced Interrupt Controller (AIC)”
Removed reset value from register description sections (reset values are provided in Table 28-2 “Register Mapping”)
Table 51-2. Revision History - SAM9263 Datasheet Revision 6249M (Continued)
Date Comments