Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1066
50.1.15.3 Unexpected Delay on TD output
When SSC is configured with the following conditions:
 TCMR.STTDLY more than 0
 RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge
 RFMR.FSOS = None (input)
 TCMR.START = Receive Start
An unexpected delay of two or three system clock cycles is added to TD output.
Problem Fix/Workaround
None.
50.1.16 Pulse Width Modulation (PWM)
50.1.16.1 Zero Period
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
Problem Fix/Workaround
None.
50.1.17 System Controller
50.1.17.1 Possible Event Loss when Reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when RTT_SR is read, the
corresponding bit may be cleared. This may lead to the loss of this event.
Problem Fix/Workaround
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
50.1.18 Two-wire Interface (TWI)
50.1.18.1 Clock Divider
The value of CLDIV x 2
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
CKDIV
must be less than or
equal to 8191·
Problem Fix/Workaround
None.
50.1.18.2 Disabling Does Not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled
before disabling the TWI.
50.1.18.3 Software Reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new
transfer in READ or WRITE mode.
Problem Fix/Workaround
None.