Datasheet
1065
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
50.1.14.4 SPI: Baudrate Set to 1
When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency), and when the
fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse
is generated on output SPCK. No such pulse occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
50.1.14.5 SPI: Software Reset
If the Software reset command is performed during the same clock cycle as an event for TXRDY, there is no reset.
Problem Fix/Workaround
Perform another a software reset.
50.1.14.6 SPI: SPI Software Reset Must Be Written Twice
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly set.
Problem Fix/Workaround
None.
50.1.14.7 SPI: Chip Select and Fixed Mode
In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the
output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 register, whatever the selected Chip
select may be. For example, if CSR0 is configured for a 10-bit transfer, whereas the CSR1 is configured for an 8-
bit transfer, when a transfer is performed in Fixed mode through the PDC on Chip Select 1, the transfer is
considered to be a half-word transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field BITS of the CSR0
must be configured in 8 bits in the same way as the field BITS of the CSRy Register.
50.1.14.8 SPI: Software Reset Must be Written Twice
If a software reset (SWRST in the control register) is performed, the SPI may not work properly (the clock is
enabled before the chip select).
Problem Fix/Workaround
The SPI Control Register field, SWRST (Software Reset) needs to be written twice to be correctly set.
50.1.15 Serial Synchronous Controller (SSC)
50.1.15.1 Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge
(rising or falling) of synchro with a Start Delay equal to zero.
Problem Fix/Workaround
None.
50.1.15.2 Periodic Transmission Limitations in Master Mode
If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.