Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1064
STR r1, [r0]
;perform proc_reset and periph_reset (in the ARM pipeline)
STR r3, [r2]
END
50.1.12 SDRAM Controller
50.1.12.1 Mobile SDRAM Device Initialization Constraint
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM device initialization
may lead to data bus contention and thus external memories on the same EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this phase.
Problem Fix/Workaround
Mobile SDRAM initialization must be performed in internal SRAM.
50.1.13 Static Memory Controller (SMC)
50.1.13.1 SMC Chip Select Parameters Modification
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters while fetching the code from a memory on
CS0, may lead to unpredictable behavior.
Problem Fix/Workaround:
The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a
memory connected to another Chip Select.
50.1.14 Serial Peripheral Interface (SPI)
50.1.14.1 SPI: Pulse Generation on SPCK
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows:
 The Baudrate is odd and different from 1.
 The Polarity is set to 1.
 The Phase is set to 0.
Problem Fix/Workaround
None.
50.1.14.2 SPI: Bad PDC Behavior when CSAAT = 1 and SCBR = 1
If the SPI2 is programmed with CSAAT = 1, SCBR (baudrate) = 1 and two transfers are performed consecutively
on the same slave with an IDLE state between them, the second data is sent twice.
Problem Fix/Workaround
None. The combination CSAAT = 1 and SCBR = 1 is forbidden.
50.1.14.3 SPI: LASTXFER (Last Transfer) Behavior
In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the data written in
the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a "1" in bit 24 (LASTXFER bit) of the
SPI_TDR, the Chip Select rises as soon as the TXEMPTY flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when PDC Mode is required and CS has to be maintained between transfers.