Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1062
50.1.9.4 Data Write Operation and Number of Bytes
The Data Write operation with a number of bytes less than 12 is impossible.
Problem Fix/Workaround
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT
field are used to specify the real count number.
50.1.9.5 Flag Reset is not correct in half duplex mode
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect.
These flags are reset correctly after a PDC channel enable.
Problem Fix/Workaround
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the PDC channel by
writing PDC_TXTEN or PDC_RXTEN.
50.1.10 NTRST
50.1.10.1 NTRST: Device does not boot correctly due to power-up sequencing issue
The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is powered by VDDCORE
power supply (1.2V).
During the power-up sequence, if VDDIOP power supply is not established whereas the VDDCORE Power-On
Reset output is released, the NTRST signal is not correctly asserted. This leads to a bad reset of the Embedded
Trace Macrocell (ETM9). The ARM processor then enters debug state and the device does not boot correctly.
Problem Fix/Workaround
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes place in all cases.
2. Connect NTRST to GND if no debug capabilities are required.
50.1.11 Reset Controller (RSTC)
50.1.11.1 RSTC: ERSTL Default Value is 1
The default value of ERSTL field in RSTC_MR has been changed from 0x0 to 0x1. This means that the NRST line
rises four cycles after backup_nreset.
Problem Fix/Workaround
None.
50.1.11.2 RSTC: Reset during SDRAM Accesses
When a user reset, watchdog reset, or software reset occurs during SDRAM read access, the SDRAM clock is
turned off while data is ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.
If the user reset, watchdog reset, or software reset is programmed to assert a general reset, the data maintained
by the SDRAM leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
 NAND Flash boot functionality, if the system boots out of internal ROM.
 NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
Problem Fix/Workaround
1. Avoid user reset, watchdog reset, or software reset to generate a system reset.
2. Trap the user reset, watchdog reset, or software reset with an interrupt.
In the interrupt routine, power down the SDRAM properly and perform Peripheral and Processor Reset with
software in assembler.