Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1060
EMACB master interface releases the AHB bus between two transfers.
EMACB has the highest priority.
If we are in a state where EMACB RX and TX FIFOs have requests pending, the following sequence occurs:
1. EMACB RX FIFO write (burst 4)
2. EMACB release the AHB bus
3. The AHB matrix can grant an another master (ARM I or D for example)
4. AHB matrix re-arbitration (finish at least the current word/halfword/byte)
5. The AHB matrix grants the EMACB
6. The EMACB TX FIFO read (burst 4)
In a case of a slow memory and/or a special operation such as SDRAM refresh or SDRAM bank opening /closing,
there may be TX underrun (latency min 960 ns).
Problem Fix/Workaround
Reduce re-arbitration time between RX and TX EMACB transfer by using internal SRAM (or another slave with a
short access time) for transmit buffers and descriptors.
50.1.8 LCD
50.1.8.1 LCD Screen Shifting After a Reset
When a FIFO underflow occurs, a reset of the DMA and FIFO pointers is necessary. Performing the following
sequence:
 DMA disable
 Wait for DMABUSY
 DMA reset
 DMA enable
leads to well reset DMA pointers but not FIFO pointers, the displayed image is shifted.
Problem Fix/Workaround
Apply the following sequence:
 LCD power off
 DMA disable
 Wait for DMABUSY
 DMA reset
 LCD power on
 DMA enable
50.1.8.2 LCD Periodic Bad Pixels
LCD periodic bad pixels is due to misaligned DMA base address in frame buffer. LCD DMA performs bursts to
read memory. These bursts must not cross 1 KB AMBA boundary.
Problem Fix/Workaround
The burst size in 32-bit words is programmed by field BRSTLN in DMAFRMCFG register.
The LCD DMA Base Address is programmed in DMABADDR1 register.