Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1050
46.11.3 MCI
The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data
bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content
(empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application
(user programming).
These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card.
Figure 46-15. MCI Timing Diagram
Table 46-40. MCI Timings
Symbol Parameter Min Max Unit
11/t
CLK
= CLK frequency at Data transfer Mode (PP) 0 51 MHz
2 Input hold time 1.5 ns
3 Input setup time -0.1 ns
4 Output hold time -1.0 ns
5 Output setup time 1/t
CLK
- 2.8 ns
Valid Data
Valid Data
Valid Data
Valid Data
Bus Clock
CMD_DAT Input
CMD_DAT Output
1
2 3
4
5
6