Datasheet

1047
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
46.11.1.2 Timing Conditions
Timings are given assuming a capacitance load on MISO, SPCK and MOSI as defined in Table 46-35.
46.11.1.3 Timing Extraction
In Figure 46-10 ”SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)” and Figure
46-11 ”SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)” the MOSI line shifting edge is
represented with a hold time = 0. However, it is important to note that for this device, the MISO line is sampled
prior to the MOSI line shifting edge. As shown in Figure 46-9 ”MISO Capture in Master Mode”, the device sampling
point extends the propagation delay (t
p
) for slave and routing delays to more than half the SPI clock period,
whereas the common sampling point allows only less than half the SPI clock period.
As an example, an SPI Slave working in Mode 0 is safely driven if the SPI Master is configured in Mode 0.
Figure 46-9. MISO Capture in Master Mode
Figure 46-10. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
Table 46-35. Capacitance Load for MISO, SPCK and MOSI (product dependent)
Supply Max Min
3.3V 40 pF 5 pF
1.8V 20 pF 5 pF
MISO
(slave answer)
SPCK
(generated
by the master)
MISO cannot be provided
before the edge
Bit N Bit N+1
0 < delay < SPI
0
or SPI
3
Bit N
Internal
shift register
Safe margin,
always > 0
Common sampling point
Device sampling point
t
p
Extended t
p
SPCK
MISO
MOSI
SPI
2
SPI
0
SPI
1