Datasheet

1041
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
46.9.4.2 External Bus Interface 1 Timings
SDRAMC
14
Bank Change after SDCK Rising Edge 4.6 4.6 5.0 4.2 ns
SDRAMC
15
CAS Low before SDCK Rising Edge 4.7 4.8 3.0 2.6 ns
SDRAMC
16
CAS High after SDCK Rising Edge 4.5 4.5 4.9 4.1 ns
SDRAMC
17
DQM Change before SDCK Rising Edge 2.8 3.2 1.1 0.9 ns
SDRAMC
18
DQM Change after SDCK Rising Edge 4.2 4.2 4.6 3.8 ns
SDRAMC
19
D0–D15 in Setup before SDCK Rising Edge 2.5 1.7 2.6 1.8 ns
SDRAMC
20
D0–D15 in Hold after SDCK Rising Edge -0.1 -0.1 -0.1 -0.1 ns
SDRAMC
21
D16–D31 in Setup before SDCK Rising Edge 3.3 2.3 3.4 2.4 ns
SDRAMC
22
D16–D31 in Hold after SDCK Rising Edge 0.1 0.1 0.2 0.2 ns
SDRAMC
23
SDWE Low before SDCK Rising Edge 4.1 4.4 2.4 2.1 ns
SDRAMC
24
SDWE High after SDCK Rising Edge 4.8 4.8 5.2 4.3 ns
SDRAMC
25
D0–D15 Out Valid before SDCK Rising Edge 2.9 3.4 1.4 1.2 ns
SDRAMC
26
D0–D15 Out Valid after SDCK Rising Edge 3.8 3.8 4.5 3.8 ns
SDRAMC
27
D16–D31 Out Valid before SDCK Rising Edge 4.1 4.5 2.4 2.2 ns
SDRAMC
28
D16–D31 Out Valid after SDCK Rising Edge 3.4 3.4 4.4 3.6 ns
Table 46-30. SDRAMC Clock Signal
Symbol Parameter
Max
Unit1.8V Supply 3.3V Supply
1/(t
CPSDCK
) SDRAM Controller Clock Frequency 100 100 MHz
Table 46-31. SDRAMC Signals
Symbol Parameter
Max
Unit
VDDCORE Supply
(VDDIOM 1.8V)
VDDCORE Supply
(VDDIOM 3.3V)
1.08V 1.3V 1.08V 1.3V
SDRAMC
1
SDCKE High before SDCK Rising Edge 3.6 3.9 2.3 2.0 ns
SDRAMC
2
SDCKE Low after SDCK Rising Edge 4.3 4.4 5.1 4.3 ns
SDRAMC
3
SDCKE Low before SDCK Rising Edge 3.8 4.1 2.2 1.8 ns
SDRAMC
4
SDCKE High after SDCK Rising Edge 3.7 3.9 4.8 4 ns
SDRAMC
5
SDCS Low before SDCK Rising Edge 3.7 4.0 2.0 1.7 ns
SDRAMC
6
SDCS High after SDCK Rising Edge 4.2 4.2 5.0 4.2 ns
SDRAMC
7
RAS Low before SDCK Rising Edge 4.7 4.8 3.1 2.6 ns
Table 46-29. SDRAMC Signals (Continued)
Symbol Parameter
Max
Unit
VDDCORE Supply
(VDDIOM 1.8V)
VDDCORE Supply
(VDDIOM 3.3V)
1.08V 1.3V 1.08V 1.3V