Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1040
46.9.4 SDRAMC Signals
Timings are given assuming a capacitance load on data, control and address pads as defined in Table 46-26 as
well as on the SDCK pad as defined in Table 46-27.
46.9.4.1 External Bus Interface 0 Timings
Table 46-26. Capacitance Load on data, control and address pads
I/O Supply C
LOAD
Max
3.3V 50 pF
1.8V 30 pF
Table 46-27. Capacitance Load on SDCK pad
I/O Supply C
LOAD
Max
3.3V 10 pF
1.8V 10 pF
Table 46-28. SDRAMC Clock Signal
Symbol Parameter
Max
Unit
VDDCORE Supply
(VDDIOM 1.8V)
VDDCORE Supply
(VDDIOM 3.3V)
1.08V 1.3V 1.08V 1.3V
1/(t
CPSDCK
) SDRAM Controller Clock Frequency 100 120 100 120 MHz
Table 46-29. SDRAMC Signals
Symbol Parameter
Max
Unit
VDDCORE Supply
(VDDIOM 1.8V)
VDDCORE Supply
(VDDIOM 3.3V)
1.08V 1.3V 1.08V 1.3V
SDRAMC
1
SDCKE High before SDCK Rising Edge 4.4 4.6 3.1 2.7 ns
SDRAMC
2
SDCKE Low after SDCK Rising Edge 4.6 4.6 5.2 4.4 ns
SDRAMC
3
SDCKE Low before SDCK Rising Edge 4.4 4.6 2.7 2.3 ns
SDRAMC
4
SDCKE High after SDCK Rising Edge 4.6 4.6 5.0 4.2 ns
SDRAMC
5
SDCS Low before SDCK Rising Edge 4.4 4.5 2.7 2.3 ns
SDRAMC
6
SDCS High after SDCK Rising Edge 4.7 4.7 5.1 4.3 ns
SDRAMC
7
RAS Low before SDCK Rising Edge 4.0 4.3 2.3 2.1 ns
SDRAMC
8
RAS High after SDCK Rising Edge 4.7 4.7 5.1 4.3 ns
SDRAMC
9
SDA10 Change before SDCK Rising Edge 3.8 4.2 2.5 2.3 ns
SDRAMC
10
SDA10 Change after SDCK Rising Edge 4.6 4.6 5.1 4.3 ns
SDRAMC
11
Address Change before SDCK Rising Edge 2.9 3.3 2.2 1 ns
SDRAMC
12
Address Change after SDCK Rising Edge 4.3 4.3 4.7 3.9 ns
SDRAMC
13
Bank Change before SDCK Rising Edge 2.8 3.2 1.1 0.9 ns