Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
1002
45.3.4.4 FIFO and DMA Features
Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted
pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and
triggers a relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified
length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list
operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or
more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each
FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation
at another frame buffer address. The FBD is defined by a series of two words. The first one defines the current
frame buffer address, and the second defines the next FBD memory location. This DMA transfer mode is only
available for preview datapath and is configured in the ISI_PPFBD register that indicates the memory location of
the first FBD.
The primary FBD is programmed into the camera interface controller. The data to be transferred described by an
FBD requires several burst access. In the example below, the use of 2 ping-pong frame buffers is described.
45.3.4.5 Example
The first FBD, stored at address 0x30000, defines the location of the first frame buffer.
Destination Address: frame buffer ID0 0x02A000
Next FBD address: 0x30010
Second FBD, stored at address 0x30010, defines the location of the second frame buffer.
Destination Address: frame buffer ID1 0x3A000
Transfer width: 32 bit
Next FBD address: 0x30000, wrapping to first FBD.
Using this technique, several frame buffers can be configured through the linked list. Figure 45-6 illustrates a
typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1,
frame n+2 is mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2
encoded frame is stored in a dedicated memory space.