SAM9263 Atmel | SMART ARM-based Embedded MPU DATASHEET Description The Atmel ® | SMART ARM926-based SAM9263 32-bit microprocessor is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent bottlenecks, thus guaranteeing maximum performance.
Features 2 ARM926EJ-S™ ARM® Thumb® Processor ̶ DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration ̶ 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer ̶ 220 MIPS at 200 MHz ̶ Memory Management Unit ̶ EmbeddedICE™, Debug Communication Channel Support ̶ Mid-level Implementation Embedded Trace Macrocell™ Bus Matrix ̶ Nine 32-bit-layer Matrix, Allowing a Total of 28.
̶ Periodic Interval Timer, Watchdog Timer and Double Real-time Timer Reset Controller (RSTC) ̶ Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) ̶ Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) ̶ 32.
One 4-channel 16-bit PWM Controller (PWM) One Two-wire Interface (TWI) ̶ Master Mode Support, All Two-wire Atmel EEPROMs Supported IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Package ̶ 324-ball TFBGA - 15 x 15 x 1.2 mm, 0.
SAM9263 Block Diagram TST EBI0_ JTAG Boundary Scan System Controller HD HDPA M HD A HDPB M B SLAVE NT TDRS TDI T TMO TC S K MASTER TC TS LK TPYN C TPS0 K –T BM 0–TPS2 S PK 15 LC LCDD 0 LCDV –L S C LCDH YN DD S LCDD YNC 23 O LCDD TCC DCEN K ET C ETXCK ECXEN-ER R - X ER S- ETX CK E ERXE CO ER ERE R L FC ET X0– -ER K X E X EM 0– RX DV E EMDC TX 3 3 EF DIO 10 0 SAM9263 Block Diagram L Figure 1-1. RT JT CK AG SE 1. Transc. Transc.
2. Signal Description Table 2-1 gives details on the signal name classified by peripheral. Table 2-1. Signal Description List Signal Name Function Type Active Level Comments Power Supplies VDDIOM0 EBI0 I/O Lines Power Supply Power 1.65–3.6 V VDDIOM1 EBI1 I/O Lines Power Supply Power 1.65–3.6 V VDDIOP0 Peripherals I/O Lines Power Supply Power 2.7–3.6 V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65–3.6 V VDDBU Backup I/O Lines Power Supply Power 1.08–1.
Table 2-1.
Table 2-1.
Table 2-1.
Table 2-1.
3. Package and Pinout The SAM9263 is available in a 324-ball TFBGA Green-compliant package. 3.1 324-ball TFBGA Package Outline Figure 3-1 shows the orientation of the 324-ball TFBGA package. A detailed mechanical description is given in Section 47. “SAM9263 Mechanical Characteristics”. Figure 3-1. 324-ball TFBGA Pinout (Top View) TOP VIEW Pin A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A B C D E F G H J K L M N P R T U V 3.2 324-ball TFBGA Package Pinout Table 3-1.
Table 3-1.
Table 3-1.
4. Power Considerations 4.1 Power Supplies The SAM9263 device has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1. Table 4-1. SAM9263 Power Supply Pins Pin(s) Item(s) powered VDDCORE Core, including the processor Embedded memories Peripherals VDDIOM0 External Bus Interface 0 I/O lines VDDIOM1 External Bus Interface 1 I/O lines VDDIOP0 Peripheral I/O lines USB transceivers Range Typical 1.08–1.32 V 1.
4.2.1 Power-up Sequence For the first power-up, VDDCORE is to be established before VDDBU. VDDBU powers the Backup power switch; it must always be powered to ensure correct behavior. VDDCORE and VDDBU are controlled by internal POR (Power-on Reset) to guarantee that these power sources reach their target values prior to the release of POR. VDDIOM0, VDDIOM1, VDDIOP0, VDDIOP1 and VDDIOP2 must NOT be powered until VDDCORE has reached a level superior to VT+.
4.2.2 Power-down Sequence Switch off the VDDIOMx and VDDIOPx power supply prior to or at the same time as VDDCORE. No power-up or power-down restrictions apply to other power supplies. 4.3 Programmable I/O Lines Power Supplies The power supply pins VDDIOM0 and VDDIOM1 accept two voltage ranges. This allows the device to reach its maximum speed, either out of 1.8V or 3.0V external memories. The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF.
5. I/O Line Considerations 5.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 5.3.
6. Processor and Architecture 6.
One Address Decoder provided per Master ̶ 6.2.
6.2.3 Master to Slave Access In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and are shown as “–” in Table 6-3. Table 6-3.
6.
6.
7. Memories Figure 7-1.
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its master and slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 9 are directed to the EBI0 that associates these banks to the external chip selects EBI0_NCS0 to EBI0_NCS5 and EBI1_NCS0 to EBI1_NCS2.
Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes as shown in Table 7-2. This table provides the size of the Internal SRAM C according to the size of the internal SRAM A and the internal SRAM B. Table 7-2.
7.1.1.2 Internal 16 Kbyte Fast SRAM The SAM9263 integrates a 16 Kbyte SRAM, mapped at address 0x0050 0000. This SRAM is single cycle accessible at full Bus Matrix speed. 7.1.2 Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. After reset, the ROM is mapped at both addresses 0x0000_0000 and 0x0040_0000. REMAP allows the user to layout the internal SRAM bank to 0x0.
7.2 External Memories The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to Figure 7-1 on page 24. 7.2.1 External Bus Interfaces The SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. 7.2.1.
7.2.
8. System Controller The System Controller is a set of peripherals that allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds registers that are used to configure the Bus Matrix and a set of registers for the chip configuration.
8.1 System Controller Block Diagram Figure 8-1. SAM9263 System Controller Block Diagram System Controller VDDCORE Powered irq0–irq1 fiq nirq nfiq Advanced Interrupt Controller periph_irq[2..
8.2 Reset Controller Based on two Power-on-Reset cells ̶ One on VDDBU and one on VDDCORE Status of the last reset ̶ Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset Controls the internal resets and the NRST pin output ̶ 8.3 Allows shaping a reset signal for the external devices Shutdown Controller See SHDWC Section 17.2 “Embedded Characteristics”. 8.4 Clock Generator Embeds the low-power 32.
8.
8.9 General-purpose Backup Registers 8.10 Backup Power Switch 8.
Fully programmable through Set/Clear Registers Multiplexing of two peripheral functions per I/O Line For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O) 34 ̶ Input change interrupt ̶ Glitch filter ̶ Multi-drive option enables driving in open drain ̶ Programmable pull-up on each I/O line ̶ Pin data status register, supplies visibility of the level on the pin at any time Synchronous output, provides Set and Clear of several I/O lines in a single write SAM
9. Peripherals 9.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 7-1 on page 24. 9.2 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers.
Table 9-1. SAM9263 Peripheral Identifiers (Continued) Peripheral ID Note: 9.2.1 Peripheral Mnemonic Peripheral Name External Interrupt 26 LCDC LCD Controller 27 DMA DMA Controller 28 Reserved 29 UHP USB Host Port 30 AIC Advanced Interrupt Controller IRQ0 31 AIC Advanced Interrupt Controller IRQ1 Setting AIC, SYSC, UHP and IRQ0–1 bits in the clock set/clear registers of the PMC has no effect. Peripheral Interrupts and Clock Control 9.2.1.
soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is specified in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
9.3.1 PIO Controller A Multiplexing Table 9-2.
9.3.2 PIO Controller B Multiplexing Table 9-3.
9.3.3 PIO Controller C Multiplexing Table 9-4.
9.3.4 PIO Controller D Multiplexing Table 9-5.
9.3.5 PIO Controller E Multiplexing Table 9-6.
9.4 System Resource Multiplexing 9.4.1 LCD Controller The LCD Controller can interface with several LCD panels. It supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without limitation. Interfacing 24 bpp TFT panels prevents using the Ethernet MAC. 16 bpp TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD10. Using the peripheral B does not prevent using MAC lines.
9.4.9 SPI0 and MCI Interface SPI0 signals and MCI0 signals are multiplexed, as the DataFlash Card is hardware-compatible with the SDCard. Only one can be used at a time. 9.4.10 Interrupts Using IRQ0 prevents using the CAN controller. Using FIQ prevents using DMA Request 2. 9.4.11 Image Sensor Interface Using ISI in 8-bit data mode prevents using timers TIOA1, TIOB1. 9.4.12 Timers Using TIOA2 and TIOB2, in this order, prevents using SPI1’s Chip Selects [2–3].
9.5 Embedded Peripherals Overview 9.5.1 Serial Peripheral Interface 9.5.
9.5.4 9.5.5 Serial Synchronous Controller Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.
̶ 32 bits access to Data registers for each mailbox data object Uses a 16-bit time stamp on receive and transmit message ̶ ̶ Hardware concatenation of ID unmasked bitfields to speedup family ID processing 16-bit internal timer for Time Stamping and Network synchronization Programmable reception buffer length up to 16 mailbox object Priority Management between transmission mailboxes Autobaud and listening mode Low power mode and programmable wake-up on bus activity or by the application Data, Remote, Error
9.5.13 Two D Graphics Controller Acts as one Matrix Master Commands are passed through the APB User Interface Operates directly in the frame buffer of the LCD Controller ̶ Line draw ̶ Block transfer ̶ Clipping Commands queuing through a FIFO 9.5.14 Ethernet 10/100 MAC See EMAC Section 40.2 “Embedded Characteristics”. 9.5.15 Image Sensor Interface 48 ITU-R BT. 601/656 8-bit mode external interface support Support for ITU-R BT.
10. ARM926EJ-S Processor Overview 10.1 Overview The ARM926EJ-S processor is a member of the ARM9s family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density.
10.2 Block Diagram Figure 10-1. ARM926EJ-S Internal Functional Block Diagram ARM926EJ-S TCM Interface Coprocessor Interface ETM Interface DEXT Droute Data AHB Interface AHB DCACHE WDATA Bus Interface Unit RDATA ARM9EJ-S DA MMU EmbeddedICE -RT Processor Instruction AHB Interface IA AHB INSTR ICE Interface ICACHE Iroute IEXT 10.3 ARM9EJ-S Processor 10.3.
All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 10.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states.
10.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers: 31 general-purpose 32-bit registers Six 32-bit status registers Table 10-1 shows all the registers in all modes. Table 10-1.
modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer.
10.3.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are: Fast interrupt (FIQ) Normal interrupt (IRQ) Data and Prefetched aborts (Abort) Undefined instruction (Undefined) Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline.
10.3.8 ARM Instruction Set Overview The ARM instruction set is divided into: Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 10-2 gives the ARM instruction mnemonic list. Table 10-2.
10.3.9 New ARM Instruction Set Table 10-3.
10.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: Branch instructions Data processing instructions Load and Store instructions Load and Store multiple instructions Exception-generating instruction Table 10-4 gives the Thumb instruction mnemonic list. Table 10-4.
10.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: ARM9EJ-S Caches (ICache, DCache and write buffer) TCM MMU Other system options To control these features, CP15 provides 16 additional registers. See Table 10-5. Table 10-5.
10.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
10.5 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
10.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access.
mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 10.6.
Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not upto-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 10.7 Tightly-Coupled Memory Interface 10.7.
10.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture.
11. SAM9263 Debug and Test 11.1 Overview The SAM9263 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, half-rate clock mode, counters, sequencer and FIFO.
11.2 Block Diagram Figure 11-1.
11.3 Application Examples 11.3.1 Debug Environment Figure 11-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 11-2.
11.4 Debug and Test Pin Description Table 11-1.
11.5 Functional Description 11.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 11.5.2 Embedded In-circuit Emulator The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9263 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width. For further details on the Debug Unit, see Section 29.
Figure 11-4. ETM9 Block TPS-TPS0 ARM926EJ-S Bus Tracker Trace Control FIFO TPK15-TPK0 TSYNC Trace Enable, View Data TAP Controller Trigger, Sequencer, Counters Scan Chain 6 TDO TDI TMS TCK ETM9 11.5.5.2 Implementation Details This section gives an overview of the Embedded Trace resources. Three-state Sequencer The sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. The sate transition is controlled with internal events.
Table 11-2.
Figure 11-6. AMP Mictor Connector Orientation AT91SAM9263-based Application Board 38 37 2 1 Pin 1Chamfer 11.5.6 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3. Bit Number SAM9263 JTAG Boundary Scan Register (Continued) Pin Name Pin Type 258 257 Associated BSR Cells INPUT PD1 IN/OUT OUTPUT 256 CONTROL 255 INPUT 254 PD2 IN/OUT OUTPUT 253 CONTROL 252 INPUT 251 PD3 IN/OUT OUTPUT 250 CONTROL 249 INPUT 248 PD4 IN/OUT 247 OUTPUT CONTROL 246 N.C.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
Table 11-3.
11.5.7 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_C03F. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B0C • VERSION[31:28]: Product Version Number Set to 0x0.
12. SAM9263 Boot Program 12.1 Overview The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If such a file is found, code is downloaded into the internal SRAM.
12.2 Flow Diagram The Boot Program implements the algorithm in Figure 12-1. Figure 12-1.
12.3 Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. External Clock Detection 3. Switch Master Clock on Main Oscillator 4. C variable initialization 5. Main oscillator frequency detection 6. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB.
12.4 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. 12.4.
12.4.2.1 Example An example of valid vectors follows: Address Value 00 ea000006 04 eafffffe 08 ea00002f 0c eafffffe 10 eafffffe 14 00001000 18 eafffffe Code B 0x20 B 0x04 B _main B 0x0c B 0x10 Code size = 4096 bytes (less than or equal to 72 Kbytes) B 0x18 The size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct vector for his application. 12.4.
Figure 12-6. Serial DataFlash Download Start Send status command Is status OK ? No Jump to next boot solution Yes Read the first 7 instructions (28 bytes). Decode the sixth ARM vector 7 vectors (except vector 6) are LDR or Branch instruction No Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 12.
12.6 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory. The first block must be guaranteed by the manufacturer. There is no ECC check. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See “DataFlash Boot” on page 99 for more information on Valid Image Detection. 12.6.
Receive a file (R): Receive data into a file from a specified address ̶ ̶ NbOfBytes: Number of bytes in hexadecimal to receive ̶ Address: Address in hexadecimal Output: ‘>’ Go (G): Jump to a specified address and execute the code ̶ Address: Address to jump in hexadecimal ̶ Output: ‘>’ Get Version (V): Return the SAM-BA boot version ̶ Output: ‘>’ 12.7.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1.
12.7.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ® , beginning with Windows 98SE. The CDC document, available at www.usb.
12.8 Hardware and Software Constraints SAM-BA boot disposes of two blocks of internal SRAM. The first block is available for user code. Its size is 73728 bytes. The second block is used for variables and stacks. Table 12-6. User Area Address Start Address End Address Size (bytes) 0x3000000 0x312000 73728 The SD Card(1), NAND Flash and DataFlash downloaded code size must be inferior to 72 K bytes.
13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 13.2 Block Diagram Figure 13-1.
13.3 Functional Description 13.3.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer. backup_nreset: Affects all the peripherals powered by VDDBU. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin.
13.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
13.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock.
13.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during three Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise.
13.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
Figure 13-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 13.3.
13.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
13.4 Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Back-up Reset RSTC_CR Write-only – – Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read/Write – 0x0000_0000 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
13.4.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFD00 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. • EXTRST: External Reset 0: No effect.
13.4.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFD04 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
13.4.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFD08 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset.
14. Real-time Timer (RTT) 14.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 14.3 Embedded Characteristics ̶ Real-time Timer 32-bit free-running back-up Counter ̶ Integrates a 16-bit programmable prescaler running on slow clock ̶ Alarm Register capable of generating a wake-up of the system through the Shutdown Controller Block Diagram Figure 14-1.
14.4 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0.
Figure 14-2. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ...
14.5 Real-time Timer (RTT) User Interface Table 14-1.
14.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0xFFFFFD20 (0), 0xFFFFFD50 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216.
14.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0xFFFFFD24 (0), 0xFFFFFD54 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV + 1) compared with the Real-time Timer.
14.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0xFFFFFD28 (0), 0xFFFFFD58 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
14.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0xFFFFFD2C (0), 0xFFFFFD5C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR.
15. Periodic Interval Timer (PIT) 15.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 15.3 Embedded Characteristics Includes a 20-bit Periodic Counter, with less than 1 µs accuracy Includes a 12-bit Interval Overlay Counter Real Time OS or Linux®/Windows CE® compliant tick generator Block Diagram Figure 15-1.
15.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
15.5 Periodic Interval Timer (PIT) User Interface Table 15-1.
15.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFD30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
15.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFD34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
15.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFD38 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
15.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFD3C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
16. Watchdog Timer (WDT) 16.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 16.
16.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 16-2.
16.5 Watchdog Timer (WDT) User Interface Table 16-1.
16.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0xFFFFFD40 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
16.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0xFFFFFD44 Access: Read/Write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
16.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0xFFFFFD48 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
17. Shutdown Controller (SHDWC) 17.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 17.2 Embedded Characteristics 17.3 Shutdown and Wake-up logic ̶ Software programmable assertion of the SHDN pin ̶ Deassertion Programmable on a WKUP pin level change or on alarm Block Diagram Figure 17-1.
17.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system.
17.7 Shutdown Controller (SHDWC) User Interface Table 17-2.
17.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFD10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0: No effect. 1: If KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
17.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFD14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 RTTWKEN 15 14 13 12 11 – 10 – 9 – 8 – 5 4 3 – 2 – 1 CPTWK1 7 6 CPTWK0 0 WKMODE0 • WKMODE0: Wake-up Mode 0 Value Wake-up Input Transition Selection 0 0 None.
17.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFD18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 RTTWK 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0: No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. 1: At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
18. General Purpose Backup Registers (GPBR) 18.1 Overview The System Controller embeds 20 general-purpose backup registers. 18.2 General Purpose Backup Registers (GPBR) User Interface Table 18-1. Offset 0x0 ... 0x4C Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 19 SYS_GPBR 19 Access Reset Read/Write – ... ...
18.2.
19. SAM9263 Bus Matrix 19.1 Description Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 9 AHB Masters to 7 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
19.4 Arbitration The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, allowing to arbitrate each slave differently. The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and this for each slave: 1. Round-Robin Arbitration (the default) 2.
19.4.2 Round-Robin Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master’s requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a round-robin manner.
19.5 Bus Matrix User Interface Table 19-1.
19.5.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...MATRIX_MCFG8 Address: 0xFFFFEC00 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – – – ULBT • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
19.5.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...MATRIX_SCFG6 Address: 0xFFFFEC40 Access: Read/Write 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 18 – FIXED_DEFMSTR 25 24 ARBT 17 16 DEFMSTR_TYPE 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SLOT_CYCLE • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
19.5.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...
19.5.4 Bus Matrix Priority Registers B For Slaves Name: MATRIX_PRBS0...
19.5.5 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0xFFFFED00 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RCB8 7 6 5 4 3 2 1 0 RCB7 RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 • RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master.
19.6 Chip Configuration User Interface Table 19-2.
19.6.
19.6.2 EBI0 Chip Select Assignment Register Name: EBI0_CSA Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – VDDIOMSEL 15 14 13 12 11 10 9 8 – – – – – – – EBI0_DBPUC 7 6 5 4 3 2 1 0 – – EBI0_CS5A EBI0_CS4A EBI0_CS3A – EBI0_CS1A – • EBI0_CS1A: EBI0 Chip Select 1 Assignment 0: EBI0 Chip Select 1 is assigned to the Static Memory Controller.
19.6.3 EBI1 Chip Select Assignment Register Name: EBI1_CSA Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – VDDIOMSEL 15 14 13 12 11 10 9 8 – – – – – – – EBI1_DBPUC 7 6 5 4 3 2 1 0 – – – – EBI1_CS2A – EBI1_CS1A – • EBI1_CS1A: EBI1 Chip Select 1 Assignment 0: EBI1 Chip Select 1 is assigned to the Static Memory Controller. 1: EBI1 Chip Select 1 is assigned to the SDRAM Controller.
20. External Bus Interface (EBI) 20.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM.
20.2 Block Diagram 20.2.1 External Bus Interface 0 Figure 20-1 shows the organization of the External Bus Interface 0. Figure 20-1.
20.2.2 External Bus Interface 1 Figure 20-2 shows the organization of the External Bus Interface 1. Figure 20-2.
20.3 I/O Lines Description Table 20-1.
Table 20-2.
Table 20-3.
Table 20-4. EBI Pins and External Static Devices Connections (Continued) Pins of the SMC Interfaced Device Signals: EBI0_, EBI1_ 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices NWR3/NBS3 – – – WE(2) Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. NWRx enables corresponding byte x writes. (x = 0, 1, 2 or 3) 3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4.
Table 20-5.
20.3.2 Connection Examples Figure 20-3 shows an example of connections between the EBI and external devices. Figure 20-3.
20.4 Product Dependencies 20.4.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 20.
20.5.6 CompactFlash Support (EBI0 only) The External Bus Interface 0 integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address space. Programming the EBI0_CS4A and/or EBI0_CS5A bit(s) of the EBI0 Chip Select Assignment Register to the appropriate value enables this logic. For details on this register, refer to Section 19.6 “Chip Configuration User Interface”.
20.5.6.2 CFCE1 and CFCE2 Signals To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS4 or NCS5). The DBW field in the SMC Mode Register corresponding to the NCS4 and/or NCS5 address space must be set as shown in Table 20-7 to enable the required access type.
20.5.6.3 Read/Write Signals In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 20-5 demonstrates a schematic representation of this logic.
20.5.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 20-9 and Table 20-10 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 20-9 are strictly dedicated to the CompactFlash interface as soon as the EBI0_CS4A and/or EBI0_CS5A (bit)s of the EBI0 Chip Select Assignment Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices.
20.5.6.5 Application Example Figure 20-6 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus.
20.5.7 NAND Flash Support External Bus Interfaces 0 and 1 integrate circuitry that interfaces to NAND Flash devices. 20.5.7.1 External Bus Interface 0 The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the EBI0_CS3A bit in the EBI0 Chip Select Assignment Register to the appropriate value enables the NAND Flash logic. For details on this register, refer to Section 19.6 “Chip Configuration User Interface”.
20.5.7.3 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines.
20.6 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer website to check current device availability. 20.6.1 16-bit SDRAM 20.6.1.1 Hardware Configuration - 16-bit SDRAM D[0..15] A[0..
20.6.2 32-bit SDRAM 20.6.2.1 Hardware Configuration - 32-bit SDRAM D[0..31] A[0..14] (Not used A12) U1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 SDA10 BA0 BA1 A14 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE SDCKE 37 SDCK 38 1%6 1%6 15 39 CAS RAS 17 18 SDWE 16 19 SDCS_NCS1 U2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
20.6.3 8-bit NAND Flash 20.6.3.1 Hardware Configuration - 8-bit NAND Flash D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
20.6.4 16-bit NAND Flash 20.6.4.1 Hardware Configuration - 16-bit NAND Flash D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
20.6.5 NOR Flash on NCS0 20.6.5.1 Hardware Configuration - NOR Flash on NCS0 D[0..15] A[1..
20.6.6 CompactFlash 20.6.6.1 Hardware Configuration - CompactFlash MEMORY & I/O MODE D[0..
20.6.6.2 Software Configuration - CompactFlash The following configuration has to be performed: Assign the EBI CS4 and/or EBI CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI0_CS4A or/and EBI0_CS5A in the EBI0 Chip Select Assignment Register located in the bus matrix memory space. The address line A23 is to select I/O (A23 = 1) or Memory mode (A23 = 0) and the address line A22 for REG function.
20.6.7 CompactFlash True IDE 20.6.7.1 Hardware Configuration - CompactFlash True IDE TRUE IDE MODE D[0..
20.6.7.2 Software Configuration - CompactFlash True IDE The following configuration has to be performed: Assign the EBI CS4 and/or EBI CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI0_CS4A or/and EBI0_CS5A in the EBI0 Chip Select Assignment Register located in the bus matrix memory space. The address line A21 is to select Alternate True IDE (A21 = 1) or True IDE (A21 = 0) modes.
21. Static Memory Controller (SMC) 21.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parameterizable.
21.4 Application Example 21.4.1 Hardware Interface Figure 21-1.
21.5 Product Dependencies 21.5.1 I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. 21.6 External Memory Mapping The SMC provides up to 26 address lines, A[25:0].
Figure 21-3. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Figure 21-4. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Figure 21-5.
21.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
Figure 21-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) D[15:0] D[15:0] D[31:16] A[25:2] SMC A[23:0] NWE Write Enable NBS0 Low Byte Enable NBS1 High Byte Enable NBS2 NBS3 Read Enable NRD Memory Enable NCS[3] D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable 21.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used.
21.8 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines. 21.8.
21.8.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD, as well as NRD_CYCLE = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
21.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 21.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first.
21.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 21-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.
Figure 21-12. Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NCS_WR_PULSE NWE_HOLD NCS_WR_HOLD NWE_CYCLE 21.8.3.3 Write Cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
21.8.3.4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 21-13). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 21-13.
21.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1) Figure 21-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 21-14. WRITE_MODE = 1.
21.8.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
21.9 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 21.9.1 Chip Select Wait States The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one.
21.9.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
Figure 21-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD no hold no setup D[31:0] write cycle (WRITE_MODE = 0) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Figure 21-19.
21.9.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State.
21.10.1 READ_MODE Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.
21.10.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 21-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
21.10.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted.
Figure 21-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 write2 controlling signal (NWE) write2 setup = 1 TDF_CYCLES = 4 D[31:0] 2 TDF WAIT STATES read1 cycle TDF_CYCLES = 4 write2 cycle TDF_MODE = 0 (optimization disabled) Read to Write Chip Select Wait State Wait State Figure 21-25.
21.11 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select.
Figure 21-27.
21.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 21-28 and Figure 21-29. After deassertion, the access is completed: the hold step of the access is performed.
Figure 21-29.
21.11.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
21.12 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been configured to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
21.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 21-32. The external device may not be fast enough to support such timings. Figure 21-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 21-32.
Figure 21-33.
21.13 Asynchronous Page Mode The SMC supports asynchronous burst reads in Page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
In Page mode, the programming of the read timings is described in Table 21-7. Table 21-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
Figure 21-35.
21.14 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 21-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 21-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 21-8.
21.14.1 SMC Setup Register Name: SMC_SETUP[0..
21.14.2 SMC Pulse Register Name: SMC_PULSE[0..
21.14.3 SMC Cycle Register Name: SMC_CYCLE[0..
21.14.4 SMC Mode Register Name: SMC_MODE[0..
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. • BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
22. SDRAM Controller (SDRAMC) 22.1 Description The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location.
22.3 Application Example 22.3.1 Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register. The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user. Table 222 to Table 22-7 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.
22.3.1.2 16-bit Memory Data Bus Width Table 22-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 Bk[1:0] 13 12 11 10 9 8 7 6 Row[10:0] Bk[1:0] 4 3 2 1 M0 Column[9:0] Row[10:0] 0 M0 Column[8:0] Row[10:0] Bk[1:0] 5 Column[7:0] Row[10:0] Bk[1:0] Table 22-6.
22.4 Product Dependencies 22.4.1 SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register. 3.
Figure 22-1. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command 22.4.2 I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function.
22.5 Functional Description 22.5.1 SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out.
22.5.2 SDRAM Controller Read Cycle The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command.
22.5.3 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 22-4 below. Figure 22-4.
22.5.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles.
22.5.5.1 Self-refresh Mode This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode.
22.5.5.2 Low-power Mode This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation).
22.5.5.3 Deep Power-down Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (See “SDRAM Device Initialization” on page 230). This is described in Figure 22-8. Figure 22-8.
22.6 SDRAM Controller (SDRAMC) User Interface Table 22-8.
22.6.1 SDRAMC Mode Register Name: SDRAMC_MR Address: 0xFFFFE200 (0), 0xFFFFE800 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 MODE • MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. Value Description 0 0 0 Normal mode. Any access to the SDRAM is decoded normally.
22.6.2 SDRAMC Refresh Timer Register Name: SDRAMC_TR Address: 0xFFFFE204 (0), 0xFFFFE804 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 COUNT 3 2 COUNT • COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
22.6.3 SDRAMC Configuration Register Name: SDRAMC_CR Address: 0xFFFFE208 (0), 0xFFFFE808 (1) Access: Read/Write 31 30 29 28 27 26 TXSR 23 22 21 20 19 18 TRCD 15 14 13 6 12 11 10 17 16 9 8 TWR 5 CAS 4 NB 3 2 NR • NC: Number of Column Bits Reset value is 8 column bits. Value Column Bits 0 0 8 0 1 9 1 0 10 1 1 11 • NR: Number of Row Bits Reset value is 11 row bits.
• DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. • TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. • TRC: Row Cycle Delay Reset value is seven cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0 and 15. • TRP: Row Precharge Delay Reset value is three cycles.
22.6.4 SDRAMC Low Power Register Name: SDRAMC_LPR Address: 0xFFFFE210 (0), 0xFFFFE810 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 9 7 – 6 5 PASR TIMEOUT DS 4 3 – 8 TCSR 2 – 1 0 LPCB • LPCB: Low-power Configuration Bits Value Description 00 Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.
22.6.5 SDRAMC Interrupt Enable Register Name: SDRAMC_IER Address: 0xFFFFE214 (0), 0xFFFFE814 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Interrupt Enable 0: No effect. 1: Enables the refresh error interrupt.
22.6.6 SDRAMC Interrupt Disable Register Name: SDRAMC_IDR Address: 0xFFFFE218 (0), 0xFFFFE818 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Interrupt Disable 0: No effect. 1: Disables the refresh error interrupt.
22.6.7 SDRAMC Interrupt Mask Register Name: SDRAMC_IMR Address: 0xFFFFE21C (0), 0xFFFFE81C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Interrupt Mask 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled.
22.6.8 SDRAMC Interrupt Status Register Name: SDRAMC_ISR Address: 0xFFFFE220 (0), 0xFFFFE820 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status (cleard on read) 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read.
22.6.
23. Error Correction Code Controller (ECC) 23.1 Description NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data.
23.3 Functional Description A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. The only configuration required for ECC is the NAND Flash or the SmartMedia page size (528/1056/2112/4224).
Figure 23-2.
(Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word 4th word (+) Parity Generation for 512/1024/2048/4096 16-bit Words 1st word 2nd word 3rd word Figure 23-3.
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
23.4 Error Correction Code Controller (ECC) User Interface Table 23-1.
23.4.1 ECC Control Register Name: ECC_CR Address: 0xFFFFE000 (0), 0xFFFFE600 (1) Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • RST: RESET Parity Provides reset to current ECC by software. 1: Resets ECC Parity and ECC NParity register. 0: No effect.
23.4.2 ECC Mode Register Name: ECC_MR Address: 0xFFFFE004 (0), 0xFFFFE604 (1) Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PAGESIZE • PAGESIZE: Page Size This field defines the page size of the NAND Flash device.
23.4.3 ECC Status Register Name: ECC_SR Address: 0xFFFFE008 (0), 0xFFFFE608 (1) Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 MULERR 25 – 17 – 9 – 1 ECCERR 24 – 16 – 8 – 0 RECERR • RECERR: Recoverable Error 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. • ECCERR: ECC Error 0: No Errors Detected.
23.4.4 ECC Parity Register Name: ECC_PR Address: 0xFFFFE00C (0), 0xFFFFE60C (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 3 2 25 – 17 – 9 24 – 16 – 8 1 0 WORDADDR WORDADDR BITADDR Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
23.4.5 ECC NParity Register Name: ECC_NPR Address: 0xFFFFE010 (0), 0xFFFFE610 (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 NPARITY NPARITY • NPARITY: Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
24. DMA Controller (DMAC) 24.1 Overview The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMA data transfer.
24.3 Functional Description 24.3.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
Figure 24-2. DMAC Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer Block Block Burst Transaction AMBA Burst Transfer Figure 24-3.
Single-block DMA transfer: Consists of a single block. Multi-block DMA transfer: A DMA transfer may consist of multiple DMAC blocks. Multi-block DMA transfers are supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks. The source and destination can independently select which method to use. ̶ ̶ ̶ Linked lists (block chaining) – A linked list pointer (LLP) points to the location in system memory where the next linked list item (LLI) exists.
24.3.3 Handshaking Interface Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller. The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the AMBA bus.
Note: The transaction-complete interrupts are triggered when both single and burst transactions are complete. The same transaction-complete interrupt is used for both single and burst transactions. 24.3.3.2 Hardware Handshaking There are five hardware handshaking interfaces connected to four external DMA requests (see Table 24-1). Table 24-1.
24.3.4 DMAC Transfer Types A DMA transfer may consist of single or multi-block transfers.
Table 24-2. Programming of Transfer Types and Channel Register Update Method (DMAC State Machine Table) Transfer Type Single Block or 1 last transfer of multi-Block 2 AutoReload multi-block transfer with contiguous SAR DMAC_CTLx, LLP_S_EN RELOAD_SR LLP_D_EN RELOAD_DS DMAC_LLPx LLP.LOC = 0 (DMAC_CTLx) (DMAC_CFGx) (DMAC_CTLx) (DMAC_CFGx) Update Method Yes 0 0 0 0 None, user reprograms None (single) None (single) Yes 0 0 0 1 DMAC_CTLx, DMAC_LLPx are reloaded from initial values.
Note: Both DMAC_SARx and DMAC_DARx updates cannot be selected to be contiguous. If this functionality is required, the size of the Block Transfer (DMAC_CTLx.BLOCK_TS) must be increased. If this is at the maximum value, use Row 10 of Table 24-2 and set up the LLI.DMAC_SARx address of the block descriptor to be equal to the end DMAC_SARx address of the previous block. Similarly, set up the LLI.DMAC_DARx address of the block descriptor to be equal to the end DMAC_DARx address of the previous block.
The “Update Method” column indicates where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next block transfer when multi-block DMAC transfers are enabled. Note: In Table 24-2 on page 268, all other combinations of DMAC_LLPx.LOC = 0, DMAC_CTLx.LLP_S_EN, DMAC_CFGx.RELOAD_SR, DMAC_CTLx.LLP_D_EN, and DMAC_CFGx.RELOAD_DS are illegal, and causes indeterminate or erroneous behavior. 24.3.5.1 Programming Examples Single-block Transfer (Row 1) 1.
Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. Write the control information in the LLI.DMAC_CTLx register location of the block descriptor for each LLI in memory (see Figure 24-8 on page 274) for channel x. For example, in the register, you can program the following: 1.
15. Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripheral). The DMAC acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. 16.
Figure 24-7. Multi-Block with Linked Address for Source and Destination Blocks are Contiguous Address of Source Layer Address of Destination Layer Block 2 DAR(3) Block 2 Block 2 SAR(3) DAR(2) Block 2 Block 1 SAR(2) DAR(1) Block 1 SAR(1) Block 0 DAR(0) Block 0 SAR(0) Source Blocks Destination Blocks The DMA transfer flow is shown in Figure 24-8 on page 274.
Figure 24-8.
Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4) 1. Read the Channel Enable register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3.
7. The DMA transfer proceeds as follows: 1. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete interrupt is un-masked (DMAC_MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software.
Figure 24-10. DMA Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Block Transfer Reload SARx, DARx, CTLx Block Complete interrupt generated here DMAC transfer Complete interrupt generated here yes Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware no CTLx.
4. 5. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
the source reload bit should remain enabled to keep the DMAC in Row 7 as shown in Table 24-2 on page 268. 2. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt is masked (DMAC_MaskBlock[x] = 1’b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case, software must clear the source reload bit, DMAC_CFGx.
Figure 24-12. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destination Address Channel Enabled by software LLI Fetch Hardware reprograms DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Reload SARx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Channel Disabled by hardware Is DMAC in Row1 or Row5 of DMAC State Machine Table? no CTLx.
Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3.
7. The DMA transfer proceeds as follows: 1. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete interrupt is un-masked (DMAC_MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software.
Figure 24-14. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software Block Transfer Reload SARx, CTLx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware no CTLx.
Note: The values in the LLI.DMAC_DARx location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively.
Figure 24-15. DMA Transfer with Linked List Source Address and Contiguous Destination Address Address of Destination Layer Address of Source Layer Block 2 SAR(2) Block 2 DAR(2) Block 1 Block 1 SAR(1) DAR(1) Block 0 Block 0 DAR(0) SAR(0) Source Blocks Destination Blocks The DMA transfer flow is shown in Figure 24-16 on page 286.
Figure 24-16.
24.3.6 Disabling a Channel Prior to Transfer Completion Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Register, DMAC_ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the DMAC_ChEnReg.CH_EN register bit. The recommended way for software to disable a channel without losing data is to use the CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register (DMAC_CFGx) register. 1.
24.4 DMA Controller (DMAC) User Interface Table 24-3.
Table 24-3.
Table 24-3.
24.4.1 Channel x Source Address Register Name: DMAC_SARx Address: 0x00800000 [0], 0x00800058 [1] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADD 23 22 21 20 SADD 15 14 13 12 SADD 7 6 5 4 SADD The address offset for each channel is: [x *0x58] For example, SAR0: 0x000, SAR1: 0x058, etc.
24.4.2 Channel x Destination Address Register Name: DMAC_DARx Address: 0x00800008 [0], 0x00800060 [1] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DADD 23 22 21 20 DADD 15 14 13 12 DADD 7 6 5 4 DADD The address offset for each channel is: 0x08+[x * 0x58] For example, DAR0: 0x008, DAR1: 0x060, etc.
24.4.3 Linked List Pointer Register for Channel x Name: DMAC_LLPx Address: 0x00800010 [0], 0x00800068 [1] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 LOC 23 22 21 20 LOC 15 14 13 12 LOC 7 6 5 4 LOC The address offset for each channel is: 0x10+[x * 0x58] For example, LLP0: 0x010, LLP1: 0x068, etc. • LOC: Address of the next LLI Starting address in memory of next LLI if block chaining is enabled.
24.4.4 Control Register for Channel x Low Name: DMAC_CTLxL Address: 0x00800018 [0], 0x00800070 [1] Access: Read/Write 31 – 23 DMS 15 SRC_MSIZE 7 DINC 30 – 22 29 – 21 TT_FC 13 14 6 5 SRC_TR_WIDTH 28 LLP_S_EN 20 12 DEST_MSIZE 4 27 LLP_D_EN 19 11 3 26 25 SMS 18 17 D_SCAT_EN S_GATH_EN 10 9 SINC 2 1 DST_TR_WIDTH 24 DMS 16 SRC_MSIZE 8 DINC 0 INT_EN The address offset for each channel is: 0x18+[x * 0x58] For example, CTL0: 0x018, CTL1: 0x070, etc.
• DEST_MSIZE: Destination Burst Transaction Length Number of data items, each of width DMAC_CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. • SRC_MSIZE: Source Burst Transaction Length Number of data items, each of width DMAC_CTLx.
• SMS: Source Master Select Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from. 00: AHB master 1 01: Reserved 10: Reserved 11: Reserved • LLP_D_EN Block chaining is only enabled on the destination side if the LLP_D_EN field is high and DMAC_LLPx.LOC is non-zero. • LLP_S_EN Block chaining is only enabled on the source side if the LLP_S_EN field is high and DMAC_LLPx.LOC is non-zero.
24.4.5 Control Register for Channel x High Name: DMAC_CTLxH Address: 0x0080001C [0], 0x00800074 [1] Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 24 – 16 15 – 7 – 14 – 6 – 13 – 5 – 12 DONE 4 11 – 3 10 – 2 BLOCK_TS 9 – 1 8 – 0 • BLOCK_TS: Block Transfer Size When the DMAC is flow controller, this field is written by the user before the channel is enabled to indicate the block size.
24.4.6 Configuration Register for Channel x Low Name: DMAC_CFGxL Address: 0x00800040 [0], 0x00800098 [1] Access: Read/Write 31 RELOAD_DS 23 30 29 28 RELOAD_SR 22 21 20 MAX_ABRST 15 14 13 12 LOCK_B_L LOCK_CH_L 7 6 5 4 CH_PRIOR – 27 26 25 24 18 DS_HS_POL 10 HS_SEL_DS 2 – 17 LOCK_B 9 FIFO_EMPT 1 – 16 LOCK_CH 8 CH_SUSP 0 – MAX_ABRST 19 SR_HS_POL 11 HS_SEL_SR 3 – The address offset for each channel is: 0x40+[x * 0x58] For example, CFG0: 0x040, CFG1: 0x098, etc.
• HS_SEL_SRC: Source Software or Hardware Handshaking Select This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel. 0: Hardware handshaking interface. Software-initiated transaction requests are ignored. 1: Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored. • LOCK_CH_L: Channel Lock Level Indicates the duration over which DMAC_CFGx.
• RELOAD_DS: Automatic Destination Reload The DMAC_DARx can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.
24.4.7 Configuration Register for Channel x High Name: DMAC_CFGxH Address: 0x00800044 [0], 0x0080009C [1] Access: Read/Write 31 – 23 – 15 – 7 SRC_PER 30 – 22 – 14 29 – 21 – 13 6 – 5 – 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 4 3 PROTCTL 2 25 – 17 – 9 SRC_PER 1 FIFO_MODE DEST_PER 24 – 16 – 8 0 FCMODE • FCMODE: Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller.
24.4.8 Source Gather Register for Channel x Name: DMAC_SGRx Address: 0x00800048 [0], 0x008000A0 [1] Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 SGC 15 14 25 – 17 24 – 16 SGI 13 12 11 10 9 8 3 2 1 0 SGI 7 6 5 4 SGI The address offset for each channel is: 0x48+[x * 0x58] For example, SGR0: 0x048, SGR1: 0x0a0, etc. The DMAC_CTLx.SINC field controls whether the address increments or decrements. When the DMAC_CTLx.
24.4.9 Destination Scatter Register for Channel x Name: DMAC_DSRx Address: 0x00800050 [0], 0x008000A8 [1] Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 DSC 15 14 25 – 17 24 – 16 DSI 13 12 11 10 9 8 3 2 1 0 DSI 7 6 5 4 DSI The address offset for each channel is: 0x50+[x * 0x58] For example, DSR0: 0x050, DSR1: 0x0a8, etc. The DMAC_CTLx.DINC field controls whether the address increments or decrements. When the DMAC_CTLx.
24.4.10 Interrupt Registers The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources: IntTfr: DMA Transfer Complete Interrupt This interrupt is generated on DMA transfer completion to the destination peripheral. IntBlock: Block Transfer Complete Interrupt This interrupt is generated on DMA block transfer completion to the destination peripheral.
24.4.
24.4.
24.4.
24.4.
24.4.
24.4.16 Source Software Transaction Request Register Name: DMAC_ReqSrcReg Address: 0x00800368 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REQ_WE1 1 SRC_REQ1 24 – 16 – 8 REQ_WE0 0 SRC_REQ0 A bit is assigned for each channel in this register. DMAC_ReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.
24.4.17 Destination Software Transaction Request Register Name: DMAC_ReqDstReg Address: 0x00800370 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REQ_WE1 1 DST_REQ1 24 – 16 – 8 REQ_WE0 0 DST_REQ0 A bit is assigned for each channel in this register. DMAC_ReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.
24.4.18 Single Source Transaction Request Register Name: DMAC_SglReqSrcReg Address: 0x00800378 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REQ_WE1 1 S_SG_REQ1 24 – 16 – 8 REQ_WE0 0 S_SG_REQ0 A bit is assigned for each channel in this register. DMAC_SglReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.
24.4.19 Single Destination Transaction Request Register Name: DMAC_SglReqDstReg Address: 0x00800380 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REQ_WE1 1 D_SG_REQ1 24 – 16 – 8 REQ_WE0 0 D_SG_REQ0 A bit is assigned for each channel in this register. DMAC_SglReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.
24.4.20 Last Source Transaction Request Register Name: DMAC_LstSrcReqReg Address: 0x00800388 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 LSTSR_WE1 1 LSTSRC1 24 – 16 – 8 LSTSR_WE0 0 LSTSRC0 A bit is assigned for each channel in this register. LstSrcReqReg[n] is ignored when software handshaking is not enabled for the source of channel n.
24.4.21 Last Destination Transaction Request Register Name: DMAC_LstDstReqReg Address: 0x00800390 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 LSTDS_WE1 1 LSTDST1 24 – 16 – 8 LSTDS_WE0 0 LSTDST0 A bit is assigned for each channel in this register. LstDstReqReg[n] is ignored when software handshaking is not enabled for the source of channel n.
24.4.22 DMAC Configuration Register Name: DMAC_DmaCfgReg Address: 0x00800398 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMA_EN • DMA_EN: DMA Controller Enable 0: DMAC Disabled 1: DMAC Enabled. This register is used to enable the DMAC, which must be done before any channel activity can begin.
24.4.23 DMAC Channel Enable Register Name: DMAC_ChEnReg Address: 0x008003A0 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 CH_EN_WE1 1 CH_EN1 24 – 16 – 8 CH_EN_WE0 0 CH_EN0 • CH_ENx: 0: Disable the Channel 1: Enable the Channel Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. The DMAC_ChEnReg.
25. Peripheral DMA Controller (PDC) 25.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The PDC contains 22 channels. The full-duplex peripherals feature 21 mono directional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature 1 bi-directional channels.
25.2 Block Diagram Figure 25-1.
25.3 Functional Description 25.3.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
These status flags are described in the Peripheral Status Register. 25.3.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix.
25.4 Peripheral DMA Controller (PDC) User Interface Table 25-1.
25.4.1 Receive Pointer Register Name: PERIPH_RPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
25.4.2 Receive Counter Register Name: PERIPH_RCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
25.4.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
25.4.4 Transmit Counter Register Name: PERIPH_TCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
25.4.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
25.4.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
25.4.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
25.4.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
25.4.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
25.4.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0: PDC Receiver channel requests are disabled. 1: PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0: PDC Transmitter channel requests are disabled.
26. Clock Generator 26.1 Overview The Clock Generator is made up of two PLLs, a Main Oscillator, and a 32.768 kHz low-power Oscillator. It provides the following clocks: SLCK, the Slow Clock, which is the only permanent clock within the system MAINCK is the output of the Main Oscillator The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 27.9. However, the Clock Generator registers are named CKGR_. 26.
26.3.1 Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 26-3. The 1 k Ω resistor is only required for crystals with frequencies lower than 8 MHz. For further details on the electrical characteristics of the Main Oscillator, see Section 46.2 “DC Characteristics”. Figure 26-3. Typical Crystal Connection AT91 Microcontroller XIN XOUT GND 1K 26.3.
stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 26.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin.
Figure 26-5. Divider and PLL Block Diagram DIVB MULB Divider B MAINCK OUTB PLL B PLLBCK PLLRCB DIVA MULA Divider A OUTA PLL A PLLACK PLLRCA PLLBCOUNT PLL B Counter LOCKB PLLACOUNT PLL A Counter SLCK LOCKA 26.4.1 PLL Filter The PLL requires connection to an external second-order filter through the PLLRCA and/or PLLRCB pin. Figure 26-6 shows a schematic of these filters. Figure 26-6.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
27. Power Management Controller (PMC) 27.1 Overview The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: 27.2 MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
27.3 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 27.6 Programmable Clock Output Controller The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers.
The MULA field is the PLL A multiplier factor. This parameter can be programmed between 0 and 2047. If MULA is set to 0, PLL A will be turned off. Otherwise PLL A output frequency is PLL A input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR after CKGR_PLLAR has been written. Once CKGR_PLLAR has been written, the user is obliged to wait for the LOCKA bit to be set in the PMC_SR.
The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock. The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 0 which means that master clock is equal to slow clock. The MDIV field is used to control the Master Clock divider.
Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation.
27.8 Clock Switching Details 27.8.1 Master Clock Switching Timings Table 27-1 and Table 27-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 27-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.5 x Main Clock 0.5 x Main Clock + 4.
27.8.2 Clock Switching Waveforms Figure 27-3. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 27-4.
Figure 27-5. Change PLLA Programming Slow Clock PLLA Clock LOCK MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 27-6.
Figure 27-7.
27.9 Power Management Controller (PMC) User Interface Table 27-3.
27.9.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – – • UHP: USB Host Port Clock Enable 0: No effect. 1: Enables the 12 and 48 MHz clock of the USB Host Port. • UDP: USB Device Port Clock Enable 0: No effect.
27.9.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – PCK • PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode. • UHP: USB Host Port Clock Disable 0: No effect.
27.9.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – PCK • PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled.
27.9.4 PMC Peripheral Clock Enable Register Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0: No effect.
27.9.5 PMC Peripheral Clock Disable Register Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0: No effect.
27.9.
27.9.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The Main Oscillator is disabled. 1: The Main Oscillator is enabled. OSCBYPASS must be set to 0.
27.9.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled.
27.9.9 PMC Clock Generator PLL A Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read/Write 31 – 30 – 29 1 28 – 23 22 21 20 27 – 26 25 MULA 24 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
27.9.10 PMC Clock Generator PLL B Register Name: CKGR_PLLBR Address: 0xFFFFFC2C Access: Read/Write 31 – 30 – 29 23 22 21 28 USBDIV 20 27 – 26 25 MULB 24 19 18 17 16 10 9 8 2 1 0 MULB 15 14 13 12 11 OUTB 7 PLLBCOUNT 6 5 4 3 DIVB Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
27.9.
27.9.12 PMC Programmable Clock Register Name: PMC_PCKx Address: 0xFFFFFC40 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 7 6 5 – – – • CSS: Master Clock Selection CSS Clock Source Selection 0 0 Slow Clock is selected. 0 1 Main Clock is selected. 1 0 PLL A Clock is selected. 1 1 PLL B Clock is selected.
27.9.
27.9.
27.9.15 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – – – – MCKRDY LOCKB LOCKA MOSCS • MOSCS: MOSCS Flag Status 0: Main oscillator is not stabilized. 1: Main oscillator is stabilized. • LOCKA: PLL A Lock Status 0: PLL A is not locked 1: PLL A is locked.
27.9.
27.9.17 PLL Charge Pump Current Register Name: PMC_PLLICPR Address: 0xFFFFFC80 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – ICPPLLB 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – ICPPLLA • ICPPLLA: Charge pump current Must be set to 1. • ICPPLLB: Charge pump current Must be set to 1.
28. Advanced Interrupt Controller (AIC) 28.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and realtime overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
28.2 Block Diagram Figure 28-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 28.3 Application Block Diagram Figure 28-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 28.
28.5 I/O Line Description Table 28-1. 28.6 I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0–IRQn Interrupt 0–Interrupt n Input Product Dependencies 28.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function.
28.7 Functional Description 28.7.1 Interrupt Source Control 28.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
28.7.1.5 Internal Interrupt Source Input Stage Figure 28-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 28.7.1.6 External Interrupt Source Input Stage Figure 28-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg.
28.7.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: The time the software masks the interrupts. Occurrence, either at the processor level or at the AIC level. The execution time of the instruction in progress when the interrupt occurs. The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
28.7.2.3 Internal Interrupt Edge Triggered Source Figure 28-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 28.7.2.4 Internal Interrupt Level Sensitive Source Figure 28-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 28.7.3 Normal Interrupt 28.7.3.
28.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted.
3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: ̶ Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. ̶ De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ.
28.7.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register).
28.7.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source.
28.7.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
28.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode.
28.8 Advanced Interrupt Controller (AIC) User Interface 28.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Table 28-2. Register Mapping Offset Register Name Access Reset 0x00 Source Mode Register 0 0x04 Source Mode Register 1 AIC_SMR0 Read/Write 0x0 AIC_SMR1 Read/Write 0x0 ... ... ... ... ...
28.8.2 AIC Source Mode Register Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 4 3 2 1 0 – – – 5 SRCTYPE • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest).
28.8.3 AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
28.8.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
28.8.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
28.8.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 0 7 6 5 – – – • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
28.8.7 AIC Interrupt Pending Register Name: AIC_IPR Address: 0xFFFFF10C Access: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Pending 0: Corresponding interrupt is not pending.
28.8.8 AIC Interrupt Mask Register Name: AIC_IMR Address: 0xFFFFF110 Access: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Mask 0: Corresponding interrupt is disabled.
28.8.9 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ • NFIQ: NFIQ Status 0: nFIQ line is deactivated. 1: nFIQ line is active. • NIRQ: NIRQ Status 0: nIRQ line is deactivated. 1: nIRQ line is active.
28.8.10 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Enable 0: No effect.
28.8.11 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Disable 0: No effect.
28.8.12 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Clear 0: No effect.
28.8.13 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2–PID31: Interrupt Set 0: No effect.
28.8.14 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
28.8.15 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
28.8.16 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT • PROT: Protection Mode 0: The Protection Mode is disabled. 1: The Protection Mode is enabled. • GMSK: General Mask 0: The nIRQ and nFIQ lines are normally controlled by the AIC.
28.8.17 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2–PID31: Fast Forcing Enable 0: No effect.
28.8.18 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2–PID31: Fast Forcing Disable 0: No effect.
28.8.
29. Debug Unit (DBGU) 29.1 Description The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used standalone for general purpose serial communication.
29.3 Block Diagram Figure 29-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX R ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 29-1.
29.4 Product Dependencies 29.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 29.4.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock.
29.5.2 Receiver 29.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped.
29.5.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 29-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 29.5.2.
29.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 29-9.
29.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR.
29.5.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received.
29.5.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side.
29.6 Debug Unit (DBGU) User Interface Table 29-2.
29.6.1 Debug Unit Control Register Name: DBGU_CR Address: 0xFFFFEE00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
29.6.
29.6.
29.6.
29.6.
29.6.6 Debug Unit Status Register Name: DBGU_SR Address: 0xFFFFEE14 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0: No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
• TXBUFE: Transmission Buffer Empty 0: The buffer empty signal from the transmitter PDC channel is inactive. 1: The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0: The buffer full signal from the receiver PDC channel is inactive. 1: The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0: COMMTX from the ARM processor is inactive. 1: COMMTX from the ARM processor is active.
29.6.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Address: 0xFFFFEE18 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
29.6.8 Debug Unit Transmit Holding Register Name: DBGU_THR Address: 0xFFFFEE1C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
29.6.
29.6.10 Debug Unit Chip ID Register Name: DBGU_CIDR Address: 0xFFFFEE40 Access: Read-only 31 30 29 EXT 28 27 26 NVPTYP 23 22 21 20 19 18 ARCH 15 14 13 6 5 • VERSION: Version of the Device Current version of the device.
• NVPSIZ2 Second Nonvolatile Program Memory Size Value Size 0 0 0 0 None 0 0 0 1 8 Kbytes 0 0 1 0 16 Kbytes 0 0 1 1 32 Kbytes 0 1 0 0 Reserved 0 1 0 1 64 Kbytes 0 1 1 0 Reserved 0 1 1 1 128 Kbytes 1 0 0 0 Reserved 1 0 0 1 256 Kbytes 1 0 1 0 512 Kbytes 1 0 1 1 Reserved 1 1 0 0 1024 Kbytes 1 1 0 1 Reserved 1 1 1 0 2048 Kbytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size Value Size 0 0 0 0 Reserved 0 0 0 1 1 Kbytes
• ARCH: Architecture Identifier Value Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 01
29.6.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Address: 0xFFFFEE44 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
29.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address: 0xFFFFEE48 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0: NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1: NTRST of the ARM processor’s TAP controller is held low.
30. Parallel Input/Output Controller (PIO) 30.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
30.2 Block Diagram Figure 30-1. Block Diagram PIO Controller AIC PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Figure 30-2.
30.3 Product Dependencies 30.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
30.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 30-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 30-3.
30.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 30.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR.
30.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 30.4.
30.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register).
30.5 I/O Lines Programming Example The programing example as shown in Table 30-1 below is used to define the following configuration.
30.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 30-2.
Table 30-2. Register Mapping (Continued) Offset Register 0x007C–0x009C Reserved 0x00A0 Output Write Enable 0x00A4 0x00A8 Name Access Reset PIO_OWER Write-only – Output Write Disable PIO_OWDR Write-only – Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved Notes: 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines.
30.6.1 PIO Controller PIO Enable Register Name: PIO_PER Address: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD), 0xFFFFFA00 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: PIO Enable 0: No effect.
30.6.2 PIO Controller PIO Disable Register Name: PIO_PDR Address: 0xFFFFF204 (PIOA), 0xFFFFF404 (PIOB), 0xFFFFF604 (PIOC), 0xFFFFF804 (PIOD), 0xFFFFFA04 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: PIO Disable 0: No effect.
30.6.
30.6.4 PIO Controller Output Enable Register Name: PIO_OER Address: 0xFFFFF210 (PIOA), 0xFFFFF410 (PIOB), 0xFFFFF610 (PIOC), 0xFFFFF810 (PIOD), 0xFFFFFA10 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Enable 0: No effect.
30.6.5 PIO Controller Output Disable Register Name: PIO_ODR Address: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD), 0xFFFFFA14 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Disable 0: No effect.
30.6.6 PIO Controller Output Status Register Name: PIO_OSR Address: 0xFFFFF218 (PIOA), 0xFFFFF418 (PIOB), 0xFFFFF618 (PIOC), 0xFFFFF818 (PIOD), 0xFFFFFA18 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Status 0: The I/O line is a pure input.
30.6.7 PIO Controller Input Filter Enable Register Name: PIO_IFER Address: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD), 0xFFFFFA20 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Filter Enable 0: No effect.
30.6.8 PIO Controller Input Filter Disable Register Name: PIO_IFDR Address: 0xFFFFF224 (PIOA), 0xFFFFF424 (PIOB), 0xFFFFF624 (PIOC), 0xFFFFF824 (PIOD), 0xFFFFFA24 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Filter Disable 0: No effect.
30.6.
30.6.10 PIO Controller Set Output Data Register Name: PIO_SODR Address: 0xFFFFF230 (PIOA), 0xFFFFF430 (PIOB), 0xFFFFF630 (PIOC), 0xFFFFF830 (PIOD), 0xFFFFFA30 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Set Output Data 0: No effect.
30.6.11 PIO Controller Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD), 0xFFFFFA34 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Set Output Data 0: No effect.
30.6.
30.6.
30.6.14 PIO Controller Interrupt Enable Register Name: PIO_IER Address: 0xFFFFF240 (PIOA), 0xFFFFF440 (PIOB), 0xFFFFF640 (PIOC), 0xFFFFF840 (PIOD), 0xFFFFFA40 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Enable 0: No effect.
30.6.
30.6.
30.6.
30.6.18 PIO Multi-driver Enable Register Name: PIO_MDER Address: 0xFFFFF250 (PIOA), 0xFFFFF450 (PIOB), 0xFFFFF650 (PIOC), 0xFFFFF850 (PIOD), 0xFFFFFA50 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Multi Drive Enable 0: No effect.
30.6.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD), 0xFFFFFA54 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Multi Drive Disable 0: No effect.
30.6.
30.6.21 PIO Pull Up Disable Register Name: PIO_PUDR Address: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD), 0xFFFFFA60 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Pull Up Disable 0: No effect.
30.6.22 PIO Pull Up Enable Register Name: PIO_PUER Address: 0xFFFFF264 (PIOA), 0xFFFFF464 (PIOB), 0xFFFFF664 (PIOC), 0xFFFFF864 (PIOD), 0xFFFFFA64 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Pull Up Enable 0: No effect.
30.6.
30.6.24 PIO Peripheral A Select Register Name: PIO_ASR Address: 0xFFFFF270 (PIOA), 0xFFFFF470 (PIOB), 0xFFFFF670 (PIOC), 0xFFFFF870 (PIOD), 0xFFFFFA70 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Peripheral A Select 0: No effect.
30.6.25 PIO Peripheral B Select Register Name: PIO_BSR Address: 0xFFFFF274 (PIOA), 0xFFFFF474 (PIOB), 0xFFFFF674 (PIOC), 0xFFFFF874 (PIOD), 0xFFFFFA74 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Peripheral B Select 0: No effect.
30.6.
30.6.27 PIO Output Write Enable Register Name: PIO_OWER Address: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD), 0xFFFFFAA0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Write Enable 0: No effect.
30.6.28 PIO Output Write Disable Register Name: PIO_OWDR Address: 0xFFFFF2A4 (PIOA), 0xFFFFF4A4 (PIOB), 0xFFFFF6A4 (PIOC), 0xFFFFF8A4 (PIOD), 0xFFFFFAA4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Write Disable 0: No effect.
30.6.
31. Serial Peripheral Interface (SPI) 31.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
31.3 Application Block Diagram Figure 31-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 31.4 Signal Description Table 31-1.
31.6 Functional Description 31.6.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
Figure 31-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 31-4.
31.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
31.6.3.1 Master Mode Block Diagram Figure 31-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
31.6.3.2 Master Mode Flow Diagram Figure 31-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
31.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register.
Figure 31-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR 31.6.3.
31.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0.
31.7 Serial Peripheral Interface (SPI) User Interface Table 31-3.
31.7.1 SPI Control Register Name: SPI_CR Address: 0xFFFA4000 (0), 0xFFFA8000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI.
31.7.2 SPI Mode Register Name: SPI_MR Address: 0xFFFA4004 (0), 0xFFFA8004 (1) Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – – MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode. • PS: Peripheral Select 0: Fixed Peripheral Select. 1: Variable Peripheral Select.
• PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
31.7.3 SPI Receive Data Register Name: SPI_RDR Address: 0xFFFA4008 (0), 0xFFFA8008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
31.7.4 SPI Transmit Data Register Name: SPI_TDR Address: 0xFFFA400C (0), 0xFFFA800C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
31.7.
• TXBUFE: TX Buffer Empty 0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0: No rising edge detected on NSS pin since last read. 1: A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
31.7.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0xFFFA4014 (0), 0xFFFA8014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Enables the corresponding interrupt.
31.7.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0xFFFA4018 (0), 0xFFFA8018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Disables the corresponding interrupt.
31.7.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0xFFFA401C (0), 0xFFFA801C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
31.7.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Address: 0xFFFA4030 (0), 0xFFFA8030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT – NCPHA CPOL Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
• BITS: Bits Per Transfer (See the note below the register bitmap.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
• DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
32. Two-wire Interface (TWI) 32.1 Description The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real-time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
32.3 List of Abbreviations Table 32-2. 32.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 32-1.
32.5 Application Block Diagram Figure 32-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 32.6 I/O Lines Description Table 32-3. 32.7 I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output Product Dependencies 32.7.
32.8 Functional Description 32.8.1 Transfer format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 32-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 32-3). A high-to-low transition on the TWD line while TWCK is high defines the START condition.
32.8.3 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte.
32.8.4 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge.
32.8.5 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 32.8.5.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
32.8.5.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
Figure 32-13.
Figure 32-14.
Figure 32-15.
Figure 32-16.
Figure 32-17.
Figure 32-18.
32.9 Two-wire Interface (TWI) User Interface Table 32-4.
32.9.1 TWI Control Register Name: TWI_CR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave.
32.9.
32.9.3 TWI Internal Address Register Name: TWI_IADR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. – Low significant byte address in 10-bit mode addresses.
32.9.
32.9.5 TWI Status Register Name: TWI_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 ARBLST 8 NACK 7 UNRE 6 OVRE 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0: During the length of the current frame. 1: When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
32.9.6 TWI Interrupt Enable Register Name: TWI_IER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 UNRE 6 OVRE 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0: During the length of the current frame. 1: When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
32.9.7 TWI Interrupt Disable Register Name: TWI_IDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 UNRE 6 OVRE 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0: During the length of the current frame. 1: When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
32.9.8 TWI Interrupt Mask Register Name: TWI_IMR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 UNRE 6 OVRE 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0: During the length of the current frame. 1: When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
32.9.
32.9.
33. Universal Synchronous Asynchronous Receiver Transmitter (USART) 33.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
33.3 Application Block Diagram Figure 33-2. Application Block Diagram IrLAP PPP Serial Driver Field Bus Driver EMV Driver IrDA Driver USART 33.4 RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers I/O Lines Description Table 33-1.
33.5 Product Dependencies 33.5.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
33.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication ̶ MSB- or LSB-first ̶ 1, 1.
Figure 33-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD SCK 0 1 16-bit Counter 2 FIDI >1 3 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 33.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
Table 33-2. Baud Rate Example (OVER = 0) (Continued) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.
33.6.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
33.6.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: B is the bit rate Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 33-3. Table 33-3.
Figure 33-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 33-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 33.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
Figure 33-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
Figure 33-8 and Figure 33-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 33-8. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 Figure 33-9.
Figure 33-10. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 33.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set.
33.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 526. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
33.6.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
Table 33-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 33-7. Maximum Timeguard Length Depending on Baud Rate Baud Rate (bit/s) Bit time (µs) Timeguard (ms) 1200 833 212.50 9600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 33.6.3.
Figure 33-14 shows the block diagram of the Receiver Time-out feature. Figure 33-14. Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Q Clock 16-bit Time-out Counter 16-bit Value = STTTO Character Received Load Clear TIMEOUT 0 RETTO Table 33-8 gives the maximum time-out period for some standard baud rates. Table 33-8.
33.6.3.9 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
Figure 33-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 33-16. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 33.6.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low.
Figure 33-18 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting.
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 543 and “PAR: Parity Type” on page 544.
Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1.
33.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 33-23. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8.
33.6.5.1 IrDA Modulation For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 33-9. Table 33-9. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 kbit/s 78.13 µs 9.6 kbit/s 19.53 µs 19.2 kbit/s 9.77 µs 38.4 kbit/s 4.88 µs 57.6 kbit/s 3.26 µs 115.2 kbit/s 1.63 µs Figure 33-24 shows an example of character transmission. Figure 33-24.
33.6.5.2 IrDA Baud Rate Table 33-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 33-10. 536 IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.
33.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 33-27 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 33-27. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 33.6.
33.6.7.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 33-30. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 33-30. Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 33.6.7.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 33-31.
33.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 33-12.
33.7.1 USART Control Register Name: US_CR Address: 0xFFF8C000 (0), 0xFFF90000 (1), 0xFFF94000 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
33.7.
• PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved • CHMODE: Channel Mode CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo.
• DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
33.7.
33.7.
33.7.
33.7.6 USART Channel Status Register Name: US_CSR Address: 0xFFF8C014 (0), 0xFFF90014 (1), 0xFFF94014 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
33.7.7 USART Receive Holding Register Name: US_RHR Address: 0xFFF8C018 (0), 0xFFF90018 (1), 0xFFF94018 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
33.7.8 USART Transmit Holding Register Name: US_THR Address: 0xFFF8C01C (0), 0xFFF9001C (1), 0xFFF9401C (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
33.7.
33.7.10 USART Receiver Time-out Register Name: US_RTOR Address: 0xFFF8C024 (0), 0xFFF90024 (1), 0xFFF94024 (2) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1–65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
33.7.11 USART Transmitter Timeguard Register Name: US_TTGR Address: 0xFFF8C028 (0), 0xFFF90028 (1), 0xFFF94028 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
33.7.12 USART FI DI RATIO Register Name: US_FIDI Address: 0xFFF8C040 (0), 0xFFF90040 (1), 0xFFF94040 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
33.7.13 USART Number of Errors Register Name: US_NER Address: 0xFFF8C044 (0), 0xFFF90044 (1), 0xFFF94044 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
33.7.14 USART IrDA FILTER Register Name: US_IF Address: 0xFFF8C04C (0), 0xFFF9004C (1), 0xFFF9404C (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
34. Synchronous Serial Controller (SSC) 34.1 Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
34.3 Application Block Diagram Figure 34-2. Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 34.4 Time Slot Management Frame Management Line Interface Pin Name List Table 34-1. 34.
34.6 Functional Description This section contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
34.6.1 Clock Management The transmitter clock can be generated by: an external clock received on the TK I/O pad the receiver clock the internal clock divider The receiver clock can be generated by: an external clock received on the RK I/O pad the transmitter clock the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
34.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR.
34.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR.
34.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 566. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 567.
34.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” . The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 567. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR.
Figure 34-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 34-11.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 34.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register.
34.6.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: the event that starts the data transfer (START) the delay in number of bit periods between the start event and the first data bit (STTDLY) the length of the data (DATLEN) the number of data to be transferred for each start event (DATNB).
Figure 34-14. Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 34-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Note: 1.
34.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event.
34.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 34-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB Right Channel Left Channel Figure 34-18.
Figure 34-19.
34.8 Synchronous Serial Controller (SSC) User Interface Table 34-3.
34.8.1 SSC Control Register Name: SSC_CR Address: 0xFFF98000 (0), 0xFFF9C000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive.
34.8.2 SSC Clock Mode Register Name: SSC_CMR Address: 0xFFF98004 (0), 0xFFF9C004 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
34.8.
• START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
34.8.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0xFFF98014 (0), 0xFFF9C014 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 FSEDGE 23 – 22 21 FSOS 20 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 MSBF 6 – 5 LOOP 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
• FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
34.8.
• START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
34.8.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0xFFF9801C (0), 0xFFF9C01C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 FSEDGE 23 FSDEN 22 21 FSOS 20 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 MSBF 6 – 5 DATDEF 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
• FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
34.8.7 SSC Receive Holding Register Name: SSC_RHR Address: 0xFFF98020 (0), 0xFFF9C020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
34.8.8 SSC Transmit Holding Register Name: SSC_THR Address: 0xFFF98024 (0), 0xFFF9C024 (1) Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
34.8.
34.8.
34.8.
34.8.
34.8.13 SSC Status Register Name: SSC_SR Address: 0xFFF98040 (0), 0xFFF9C040 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty.
• RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register.
34.8.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0xFFF98044 (0), 0xFFF9C044 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect.
• RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
34.8.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0xFFF98048 (0), 0xFFF9C048 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect.
• RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
34.8.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0xFFF9804C (0), 0xFFF9C04C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled.
• RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled.
35. AC97 Controller (AC97C) 35.1 Overview The AC97 Controller is the hardware implementation of the AC97 digital controller (DC’97) compliant with AC97 Component Specification 2.2. The AC97 Controller communicates with an audio codec (AC97) or a modem codec (MC’97) via the AC-link digital serial interface. All digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the AC-link protocol.
35.3 Pin Name List Table 35-1. I/O Lines Description Pin Name Pin Description Type AC97CK 12.288-MHz bit-rate clock Input AC97RX Receiver Data (Referred as SDATA_IN in AC-link spec) Input AC97FS 48-kHz frame indicator and synchronizer Output AC97TX Transmitter Data (Referred as SDATA_OUT in AC-link spec) Output The AC97 reset signal provided to the primary codec can be generated by a PIO. 35.4 Application Block Diagram Figure 35-2.
35.5 Product Dependencies 35.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the AC97 Controller receiver, the PIO controller must be configured in order for the AC97C receiver I/O lines to be in AC97 Controller peripheral mode. Before using the AC97 Controller transmitter, the PIO controller must be configured in order for the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode. 35.5.
35.6 Functional Description 35.6.1 Protocol overview AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple input and output Pulse Code Modulation PCM audio streams, as well as control register accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots. Figure 35-3.
35.6.1.1 Slot Description 35.6.1.2 Tag Slot The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The next 12 bit positions sampled by the AC97 Controller indicate which of the corresponding 12 time slots contain valid data. The slot’s last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec.
35.6.2 AC97 Controller Channel Organization The AC97 Controller features a Codec channel and two logical channels: Channel A, Channel B. The Codec channel controls AC97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. Channel A, Channel B transfer data to/from AC97 codec. All audio samples and modem data must transit by these two channels.
35.6.2.1 AC97 Controller Setup The following operations must be performed in order to bring the AC97 Controller into an operating state: 1. Enable the AC97 Controller clock in the PMC controller. 2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (AC97C_MR). 3. Configure the input channel assignment by controlling the AC97 Controller Input Assignment Register (AC97C_ICA). 4.
In most cases, the AC97 Controller is embedded in chips that target audio player devices. In such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating system. In order to avoid these polling drawbacks, the application can perform audio streams by using PDC connected to channel A, which reduces processor overhead and increases performance especially under an operating system.
35.6.2.5 AC97 Input Frame The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used according to AC97 Controller Output Channel Assignment Register (AC97C_ICA) content.
35.6.2.10To Transmit a10-bit Sample Stored in Big Endian Format on AC-link Halfword to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR). 31 24 23 16 – 15 – 8 7 Byte0[7:0] 0 {0x00, Byte1[1:0]} Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit). 31 2423 1615 – – 10 – 9 87 Byte1 [1:0] 0 Byte0[7:0] Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}. 35.6.2.
35.6.3 Variable Sample Rate The problem of variable sample rate can be summarized by a simple example. When passing a 44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. The new AC97 standard approach calls for the addition of “on-demand” slot request flags.
35.6.4.4 Wake-up Triggered by the AC97 Codec This feature is implemented in AC97 modem codecs that need to report events such as Caller-ID and wake-up on ring. The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously (regarding AC97FS) detected by the AC97 Controller.
35.7 AC97 Controller (AC97C) User Interface Table 35-4.
35.7.1 AC97 Controller Mode Register Name: AC97C_MR Address: 0xFFFA0008 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 VRA • VRA: Variable Rate (for Data Slots 3-12) 0: Variable Rate is inactive. (48 KHz only) 1: Variable Rate is active. • WRST: Warm Reset 0: Warm Reset is inactive. 1: Warm Reset is active. • ENA: AC97 Controller Global Enable 0: No effect.
35.7.2 AC97 Controller Input Channel Assignment Register Name: AC97C_ICA Address: 0xFFFA0010 Access: Read/Write 31 – 23 30 – 22 CHID10 14 15 CHID8 7 6 29 21 13 CHID7 5 CHID5 28 CHID12 20 12 4 CHID4 27 26 19 CHID9 11 18 3 25 CHID11 17 24 16 CHID8 10 CHID6 2 9 1 CHID3 8 CHID5 0 • CHIDx: Channel ID for the input slot x CHIDx Selected Receive Channel 0x0 None. No data will be received during this slot time 0x1 Channel A data will be received during this slot time.
35.7.3 AC97 Controller Output Channel Assignment Register Name: AC97C_OCA Address: 0xFFFA0014 Access: Read/Write 31 – 23 30 – 22 CHID10 14 15 CHID8 7 6 29 21 13 CHID7 5 CHID5 28 CHID12 20 12 4 CHID4 27 26 19 CHID9 11 18 3 • CHIDx: Channel ID for the output slot x CHIDx 614 Selected Transmit Channel 0x0 None. No data will be transmitted during this slot time 0x1 Channel A data will be transferred during this slot time.
35.7.4 AC97 Controller Codec Channel Receive Holding Register Name: AC97C_CORHR Address: 0xFFFA0040 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 SDATA SDATA • SDATA: Status Data Data sent by the CODEC in the third AC97 input frame slot (Slot 2).
35.7.5 AC97 Controller Codec Channel Transmit Holding Register Name: AC97C_COTHR Address: 0xFFFA0044 Access: Write-only 31 – 23 READ 15 30 – 22 29 – 21 28 – 20 14 13 12 27 – 19 CADDR 11 26 – 18 25 – 17 24 – 16 10 9 8 3 2 1 0 CDATA 7 6 5 4 CDATA • READ: Read-write command 0: Write operation to the CODEC register indexed by the CADDR address. 1: Read operation to the CODEC register indexed by the CADDR address.
35.7.6 AC97 Controller Channel A, Channel B, Receive Holding Register Name: AC97C_CARHR, AC97C_CBRHR Address: 0xFFFA0020 Address: 0xFFFA0030 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDATA RDATA 7 6 5 4 RDATA • RDATA: Receive Data Received Data on channel x.
35.7.7 AC97 Controller Channel A, Channel B, Transmit Holding Register Name: AC97C_CATHR, AC97C_CBTHR Address: 0xFFFA0024 Address: 0xFFFA0034 Access: Write-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 TDATA TDATA 7 6 5 4 TDATA • TDATA: Transmit Data Data to be sent on channel x.
35.7.8 AC97 Controller Channel A Status Register Name: AC97C_CASR Address: 0xFFFA0028 Access: Read-only 31 – 23 – 15 RXBUFF 7 – 30 – 22 – 14 ENDRX 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 TXBUFE 3 – 26 – 18 – 10 ENDTX 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
• TXBUFE: Transmit Buffer Empty for Channel A 0: AC97C_CATCR or AC97C_CATNCR have a value other than 0. 1: Both AC97C_CATCR and AC97C_CATNCR have a value of 0. • ENDRX: End of Reception for Channel A 0: The register AC97C_CARCR has not reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. 1: The register AC97C_CARCR has reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. • RXBUFF: Receive Buffer Full for Channel A 0: AC97C_CARCR or AC97C_CARNCR have a value other than 0.
35.7.9 AC97 Controller Channel B Status Register Name: AC97C_CBSR Address: 0xFFFA0038 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
35.7.10 AC97 Controller Codec Status Register Name: AC97C_COSR Address: 0xFFFA0048 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
35.7.
• CEM: Channel A Endian Mode 0: Transferring Data through Channel A is straight forward (Little-Endian). 1: Transferring Data through Channel A from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel A Enable 0: Data transfer is disabled on Channel A. 1: Data transfer is enabled on Channel A. • PDCEN: Peripheral Data Controller Channel Enable 0: Channel A is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated.
35.7.
• CEM: Channel B Endian Mode 0: Transferring Data through Channel B is straight forward (Little-Endian). 1: Transferring Data through Channel B from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel B Enable 0: Data transfer is disabled on Channel B. 1: Data transfer is enabled on Channel B.
35.7.
35.7.14 AC97 Controller Status Register Name: AC97C_SR Address: 0xFFFA0050 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF WKUP and SOF flags in AC97C_SR are automatically cleared by a processor read operation. • SOF: Start Of Frame 0: No Start of Frame has been detected since the last read of the Status Register.
35.7.15 AC97 Codec Controller Interrupt Enable Register Name: AC97C_IER Address: 0xFFFA0054 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: No Effect. 1: Enables the corresponding interrupt.
35.7.16 AC97 Controller Interrupt Disable Register Name: AC97C_IDR Address: 0xFFFA0058 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: No Effect. 1: Disables the corresponding interrupt.
35.7.17 AC97 Controller Interrupt Mask Register Name: AC97C_IMR Address: 0xFFFA005C Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
36. Controller Area Network (CAN) 36.1 Overview The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec. CAN controller accesses are made through configuration registers.
36.2 Block Diagram Figure 36-1. CAN Block Diagram Controller Area Network CANRX CAN Protocol Controller PIO CANTX Error Counter Mailbox Priority Encoder Control & Status MB0 MB1 MCK PMC MBx (x = number of mailboxes - 1) CAN Interrupt User Interface Internal Bus 36.3 Application Block Diagram Figure 36-2. 36.
36.5 Product Dependencies 36.5.1 I/O Lines The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller. 36.5.2 Power Management The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN.
dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID. Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the MOT field of the CAN_MMRx. 36.6.2.1 Message Acceptance Procedure If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier.
When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits: unsigned int MFID0_register; MFID0_register = Get_CAN_MFID0_Register(); // Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register](); 36.6.2.2 Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID.
36.6.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR).
36.6.4 CAN 2.0 Standard Features 36.6.4.1 CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments: Figure 36-4.
SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ. If the SMP field in the CAN_BR is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point. In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2). t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) ⁄ MCK Note: The BRP field must be within the range [1, 0x7F], i.
The propagation segment time is equal to twice the sum of the signal’s propagation time on the bus line, the receiver delay and the output driver delay: Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc => PROPAG = Tprs/Tcsc - 1 = 2 The remaining time for the two phase segments is: Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc Tphs1 + Tphs2 = 12 Tcsc Because this number is even, we choose Tphs2 = Tphs1 (else we would choose Tphs2 = Tphs1 + Tcsc) Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc => PHASE1 = PHASE2
Figure 36-6.
36.6.4.5 Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags.
In Error Active Mode, the user reads: ERRA = 1 ERRP = 0 BOFF = 0 In Error Passive Mode, the user reads: ERRA = 0 ERRP = 1 BOFF = 0 In Bus Off Mode, the user reads: ERRA = 0 ERRP = 1 BOFF = 1 The CAN interrupt handler should do the following: Only enable one error mode interrupt at a time. Look at and check the REC and TEC values in the interrupt handler to determine the current state. 36.6.4.
36.6.5.1 Enabling Low-power Mode A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR is set. Depending on the corresponding mask in the CAN_IMR, an interrupt is generated while SLEEP is set. The SLEEP signal in the CAN_SR is automatically cleared once WAKEUP is set.
36.6.5.2 Disabling Low-power Mode The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller. To disable Low-power Mode, the software application must: ̶ Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC).
36.7 Functional Description 36.7.1 CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC). The CAN controller must be initialized with the CAN network parameters. The CAN_BR defines the sampling point in the bit time period.
36.7.2 CAN Controller Interrupt Handling There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. All interrupt sources can be masked by writing the corresponding field in the CAN_IDR. They can be unmasked by writing to the CAN_IER. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR.
36.7.3 CAN Controller Message Handling 36.7.3.1 Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox. 36.7.3.2 Simple Receive Mailbox A mailbox is in Receive Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled.
36.7.3.3 Receive with Overwrite Mailbox A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
Figure 36-13.
36.7.3.5 Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers.
Figure 36-15. Transmitting Messages MBx message CAN BUS MBx message MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Abort MBx message Try to Abort MBx message Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx 36.7.3.6 Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. Figure 36-16.
36.7.3.7 Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx.
case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR. Figure 36-18. Consumer Handling Message x Remote Frame CAN BUS Remote Frame Message y MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) Message y Message x 36.7.
36.7.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 36-20.
Figure 36-21.
36.8 Controller Area Network (CAN) User Interface Table 36-2.
36.8.1 CAN Mode Register Name: CAN_MR Address: 0xFFFAC000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 25 24 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 DRPT 6 TIMFRZ 5 TTM 4 TEOF 3 OVL 2 ABM 1 LPM 0 CANEN • CANEN: CAN Controller Enable 0: The CAN Controller is disabled. 1: The CAN Controller is enabled. • LPM: Disable/Enable Low Power Mode 0: Disable Low Power Mode. 1: Enable Low Power Mode.
• DRPT: Disable Repeat 0: When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1: When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
36.8.2 CAN Interrupt Enable Register Name: CAN_IER Address: 0xFFFAC004 Access: Write-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 MB15 14 MB14 13 MB13 12 MB12 11 MB11 10 MB10 9 MB9 8 MB8 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Enable 0: No effect. 1: Enable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Enable 0: No effect.
• TOVF: Timer Overflow Interrupt Enable 0: No effect. 1: Enable TOVF interrupt. • TSTP: TimeStamp Interrupt Enable 0: No effect. 1: Enable TSTP interrupt. • CERR: CRC Error Interrupt Enable 0: No effect. 1: Enable CRC Error interrupt. • SERR: Stuffing Error Interrupt Enable 0: No effect. 1: Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0: No effect. 1: Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0: No effect. 1: Enable Form Error interrupt.
36.8.3 CAN Interrupt Disable Register Name: CAN_IDR Address: 0xFFFAC008 Access: Write-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 MB15 14 MB14 13 MB13 12 MB12 11 MB11 10 MB10 9 MB9 8 MB8 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Disable 0: No effect. 1: Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0: No effect.
• TOVF: Timer Overflow Interrupt 0: No effect. 1: Disable TOVF interrupt. • TSTP: TimeStamp Interrupt Disable 0: No effect. 1: Disable TSTP interrupt. • CERR: CRC Error Interrupt Disable 0: No effect. 1: Disable CRC Error interrupt. • SERR: Stuffing Error Interrupt Disable 0: No effect. 1: Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0: No effect. 1: Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0: No effect. 1: Disable Form Error interrupt.
36.8.4 CAN Interrupt Mask Register Name: CAN_IMR Address: 0xFFFAC00C Access: Read-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 MB15 14 MB14 13 MB13 12 MB12 11 MB11 10 MB10 9 MB9 8 MB8 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Mask 0: Mailbox x interrupt is disabled. 1: Mailbox x interrupt is enabled.
• TOVF: Timer Overflow Interrupt Mask 0: TOVF interrupt is disabled. 1: TOVF interrupt is enabled. • TSTP: Timestamp Interrupt Mask 0: TSTP interrupt is disabled. 1: TSTP interrupt is enabled. • CERR: CRC Error Interrupt Mask 0: CRC Error interrupt is disabled. 1: CRC Error interrupt is enabled. • SERR: Stuffing Error Interrupt Mask 0: Bit Stuffing Error interrupt is disabled. 1: Bit Stuffing Error interrupt is enabled.
36.8.5 CAN Status Register Name: CAN_SR Address: 0xFFFAC010 Access: Read-only 31 OVLSY 30 TBSY 29 RBSY 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 MB15 14 MB14 13 MB13 12 MB12 11 MB11 10 MB10 9 MB9 8 MB8 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Event 0: No event occurred on Mailbox x. 1: An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx.
• BOFF: Bus Off Mode 0: CAN controller is not in Bus Off Mode. 1: CAN controller is in Bus Off Mode. This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal). This flag is automatically reset when above condition is not satisfied. Refer to Section 36.6.4.6 “Error Interrupt Handler” on page 642 for more information. • SLEEP: CAN controller in Low power Mode 0: CAN controller is not in low power mode. 1: CAN controller is in low power mode.
• AERR: Acknowledgment Error 0: No acknowledgment error occurred during a previous transfer. 1: An acknowledgment error occurred during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared by reading CAN_SR.
36.8.6 CAN Baudrate Register Name: CAN_BR Address: 0xFFFAC014 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 SMP 23 – 22 21 20 19 BRP 18 17 16 15 – 14 – 13 12 11 – 10 9 PROPAG 8 7 – 6 5 PHASE1 4 3 – 2 1 PHASE2 0 SJW Any modification on one of the fields of the CAN_BR must be done while CAN module is disabled. To compute the different Bit Timings, please refer to the Section 36.6.4.1 “CAN Bit Timing Configuration” on page 638.
• SMP: Sampling Mode 0: The incoming bit stream is sampled once at sample point. 1: The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. SMP Sampling Mode is automatically disabled if BRP = 0.
36.8.7 CAN Timer Register Name: CAN_TIM Address: 0xFFFAC018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TIMER15 14 TIMER14 13 TIMER13 12 TIMER12 11 TIMER11 10 TIMER10 9 TIMER9 8 TIMER8 7 TIMER7 6 TIMER6 5 TIMER5 4 TIMER4 3 TIMER3 2 TIMER2 1 TIMER1 0 TIMER0 • TIMERx: Timer This field represents the internal CAN controller 16-bit timer value.
36.8.
36.8.9 CAN Error Counter Register Name: CAN_ECR Address: 0xFFFAC020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 – 10 – 9 – 8 – 3 2 1 0 TEC 15 – 14 – 13 – 12 – 7 6 5 4 REC • REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
36.8.10 CAN Transfer Command Register Name: CAN_TCR Address: 0xFFFAC024 Access: Write-only 31 TIMRST 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 MB15 14 MB14 13 MB13 12 MB12 11 MB11 10 MB10 9 MB9 8 MB8 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x Mailbox Object Type Description Receive It receives the next message.
36.8.11 CAN Abort Command Register Name: CAN_ACR Address: 0xFFFAC028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 MB15 14 MB14 13 MB13 12 MB12 11 MB11 10 MB10 9 MB9 8 MB8 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 This register initializes several abort requests at the same time.
36.8.12 CAN Message Mode Register Name: CAN_MMRx [x=0..
36.8.13 CAN Message Acceptance Mask Register Name: CAN_MAMx [x=0..
36.8.14 CAN Message ID Register Name: CAN_MIDx [x=0..
36.8.15 CAN Message Family ID Register Name: CAN_MFIDx [x=0..
36.8.16 CAN Message Status Register Name: CAN_MSRx [x=0..
• MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0: Previous transfer is not aborted. 1: Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx Mailbox Object Type Description Receive Reserved Receive with overwrite Reserved Transmit Previous transfer has been aborted Consumer The remote frame transfer request has been aborted. Producer The response to the remote frame transfer has been aborted.
• MMI: Mailbox Message Ignored 0: No message has been ignored during the previous transfer 1: At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx. Mailbox Object Type Description Receive Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message.
36.8.17 CAN Message Data Low Register Name: CAN_MDLx [x=0..
36.8.18 CAN Message Data High Register Name: CAN_MDHx [x=0..
36.8.19 CAN Message Control Register Name: CAN_MCRx [x=0..
• MACR: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame will not be serviced. It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR.
37. Pulse Width Modulation Controller (PWM) 37.1 Overview The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
37.3 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 37-1. 37.4 I/O Line Description Name Description Type PWMx PWM Waveform Output for channel x Output Product Dependencies 37.4.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function.
37.5.1 PWM Clock Generator Figure 37-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC).
37.5.2 PWM Channel 37.5.2.1 Block Diagram Figure 37-3. Functional View of the Channel Block Diagram inputs from clock generator Channel Clock Selector Internal Counter Comparator PWMx output waveform inputs from APB bus Each of the four channels is composed of three blocks: A clock selector which selects one of the clocks provided by the clock generator described in Section 37.5.1 “PWM Clock Generator” on page 689. An internal counter clocked by the output of the clock selector.
the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
Figure 37-5.
37.5.3 PWM Controller Operations 37.5.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: Configuration of the clock generator if DIVA and DIVB are required Selection of the clock for each channel (CPRE field in the PWM_CMRx) Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx) Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
Figure 37-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
37.5.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR.
37.6 Pulse Width Modulation Controller (PWM) User Interface Table 37-2.
37.6.1 PWM Mode Register Name: PWM_MR Address: 0xFFFB8000 Access: Read/Write 31 – 30 – 29 – 28 – 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 PREB DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2–255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
37.6.2 PWM Enable Register Name: PWM_ENA Address: 0xFFFB8004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Enable PWM output for channel x.
37.6.3 PWM Disable Register Name: PWM_DIS Address: 0xFFFB8008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Disable PWM output for channel x.
37.6.4 PWM Status Register Name: PWM_SR Address: 0xFFFB800C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled.
37.6.5 PWM Interrupt Enable Register Name: PWM_IER Address: 0xFFFB8010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0: No effect. 1: Enable interrupt for PWM channel x.
37.6.6 PWM Interrupt Disable Register Name: PWM_IDR Address: 0xFFFB8014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0: No effect. 1: Disable interrupt for PWM channel x.
37.6.7 PWM Interrupt Mask Register Name: PWM_IMR Address: 0xFFFB8018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0: Interrupt for PWM channel x is disabled. 1: Interrupt for PWM channel x is enabled.
37.6.8 PWM Interrupt Status Register Name: PWM_ISR Address: 0xFFFB801C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No new channel period has been achieved since the last read of the PWM_ISR. 1: At least one new channel period has been achieved since the last read of the PWM_ISR.
37.6.9 PWM Channel Mode Register Name: PWM_CMR[0..
• CPD: Channel Update Period 0: Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1: Writing to the PWM_CUPDx will modify the period at the next period start event.
37.6.10 PWM Channel Duty Cycle Register Name: PWM_CDTY[0..3] Address: 0xFFFB8204 [0], 0xFFFB8224 [1], 0xFFFB8244 [2], 0xFFFB8264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
37.6.11 PWM Channel Period Register Name: PWM_CPRD[0..3] Address: 0xFFFB8208 [0], 0xFFFB8228 [1], 0xFFFB8248 [2], 0xFFFB8268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
37.6.12 PWM Channel Counter Register Name: PWM_CCNT[0..3] Address: 0xFFFB820C [0], 0xFFFB822C [1], 0xFFFB824C [2], 0xFFFB826C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register).
37.6.13 PWM Channel Update Register Name: PWM_CUPD[0..3] Address: 0xFFFB8210 [0], 0xFFFB8230 [1], 0xFFFB8250 [2], 0xFFFB8270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
38. Timer Counter (TC) 38.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
38.3 Block Diagram Figure 38-1.
38.5 Product Dependencies 38.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 38.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 38.5.
Figure 38-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 38-3.
38.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 38-4. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
38.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger.
MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 38-5.
38.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TIOB MTIOB TIOA MTIOA Figur
38.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 38-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 38-8. RC Compare cannot be programmed to generate a trigger in this configuration.
38.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 38-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 38-10.
38.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 38-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 38-12.
38.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 38-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 38-14.
38.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
38.7 Timer Counter (TC) User Interface Table 38-4.
38.7.1 TC Block Control Register Name: TC_BCR Address: 0xFFF7C0C0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
38.7.
38.7.3 TC Channel Control Register Name: TC_CCRx [x = 0..2] Address: 0xFFF7C000 (0)[0], 0xFFF7C040 (0)[1], 0xFFF7C080 (0)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1.
38.7.4 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x = 0..
• ETRGEDG: External Trigger Edge Selection Value Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. • WAVE 0: Capture Mode is enabled. 1: Capture Mode is disabled (Waveform Mode is enabled).
38.7.5 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x = 0..
• EEVTEDG: External Event Edge Selection Value Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection Value Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
• ACPC: RC Compare Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BE
• BSWTRG: Software Trigger Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 734 SAM9263 [DATASHEET] Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
38.7.6 TC Counter Value Register Name: TC_CVx [x = 0..2] Address: 0xFFF7C010 (0)[0], 0xFFF7C050 (0)[1], 0xFFF7C090 (0)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
38.7.7 TC Register A Name: TC_RAx [x = 0..2] Address: 0xFFF7C014 (0)[0], 0xFFF7C054 (0)[1], 0xFFF7C094 (0)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
38.7.8 TC Register B Name: TC_RBx [x = 0..2] Address: 0xFFF7C018 (0)[0], 0xFFF7C058 (0)[1], 0xFFF7C098 (0)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
38.7.9 TC Register C Name: TC_RCx [x = 0..2] Address: 0xFFF7C01C (0)[0], 0xFFF7C05C (0)[1], 0xFFF7C09C (0)[2] Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
38.7.10 TC Status Register Name: TC_SRx [x = 0..2] Address: 0xFFF7C020 (0)[0], 0xFFF7C060 (0)[1], 0xFFF7C0A0 (0)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0: No counter overflow has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high.
38.7.11 TC Interrupt Enable Register Name: TC_IERx [x = 0..2] Address: 0xFFF7C024 (0)[0], 0xFFF7C064 (0)[1], 0xFFF7C0A4 (0)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt.
38.7.12 TC Interrupt Disable Register Name: TC_IDRx [x = 0..2] Address: 0xFFF7C028 (0)[0], 0xFFF7C068 (0)[1], 0xFFF7C0A8 (0)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt.
38.7.13 TC Interrupt Mask Register Name: TC_IMRx [x = 0..2] Address: 0xFFF7C02C (0)[0], 0xFFF7C06C (0)[1], 0xFFF7C0AC (0)[2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled.
39. MultiMedia Card Interface (MCI) 39.1 Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.31, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.
39.3 Block Diagram Figure 39-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy.
39.4 Application Block Diagram Figure 39-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 9 SDCard MMC 39.5 Pin Name List Table 39-1. I/O Lines Description (1) Pin Name Pin Description Type(2) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP DAT0 of an MMC DAT[0..
39.6 Product Dependencies 39.6.1 I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 39.6.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. 39.6.
Figure 39-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK Note: 1234567 1234567 1234567 MMC1 MMC2 MMC3 When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 39-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 39-3. Table 39-3.
SD Card Bus Connections with Two Slots 1 2 3 4 5 6 78 Figure 39-7. MCDA0 - MCDA3 MCCK 1 2 3 4 5 6 78 9 MCCDA SD CARD 1 MCDB0 - MCDB3 9 MCCDB SD CARD 2 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 39-8.
39.8 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
The command ALL_SEND_CID and the fields and values for the MCI_CMDR are described in Table 39-4 and Table 39-5. Table 39-4. ALL_SEND_CID Command Description CMD Index Type Argument Response Abbreviation Command Description CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response. Table 39-5.
Figure 39-9. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR (1) Read response if required Does the command involve a busy indication? No RETURN OK Read MCI_SR 0 NOTBUSY 1 RETURN OK Note: 752 1.
39.8.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities.
Figure 39-10.
39.8.4 Write Operation In write operation, the MCI Mode Register (MCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart shows how to write a single block with or without use of PDC facilities (see Figure 39-11).
Figure 39-11.
The following flowchart shows how to manage a multiple write block transfer with the PDC (see Figure 39-12). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR). Figure 39-12.
39.9 SD/SDIO Card Operations The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
39.10 MultiMedia Card Interface (MCI) User Interface Table 39-6.
39.10.1 MCI Control Register Name: MCI_CR Address: 0xFFF80000 (0), 0xFFF84000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – PWSDIS PWSEN MCIDIS MCIEN • MCIEN: MultiMedia Interface Enable 0: No effect. 1: Enables the MultiMedia Interface if MCDIS is 0. • MCIDIS: MultiMedia Interface Disable 0: No effect.
39.10.2 MCI Mode Register Name: MCI_MR Address: 0xFFF80004 (0), 0xFFF84004 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 11 PDCMODE PDCPADV PDCFBYTE WRPROOF RDPROOF 7 6 5 4 3 PWSDIV 2 1 0 CLKDIV • CLKDIV: Clock Divider MultiMedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2 * (CLKDIV + 1)).
• PDCMODE: PDC-oriented Mode 0: Disables PDC transfer 1: Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer has been completed. • BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MCI Block Register (MCI_BLKR). Bits 16 and 17 must be set to 0 if PDCFBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used.
39.10.3 MCI Data Timeout Register Name: MCI_DTOR Address: 0xFFF80008 (0), 0xFFF84008 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DTOMUL DTOCYC • DTOCYC: Data Timeout Cycle Number Defines a number of Master Clock cycles with DTOMUL.
39.10.4 MCI SDCard/SDIO Register Name: MCI_SDCR Address: 0xFFF8000C (0), 0xFFF8400C (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 1 7 6 5 4 3 2 SDCBUS – – – – – • SDCSEL: SDCard/SDIO Slot Value SDCard/SDIO Slot 0 0 Slot A is selected.
39.10.
39.10.6 MCI Command Register Name: MCI_CMDR Address: 0xFFF80014 (0), 0xFFF84014 (1) Access: Write-only 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 – – 15 14 13 12 11 – – – MAXLAT OPDCMD 6 5 4 3 7 18 TRTYP RSPTYP 25 24 IOSPCMD 17 TRDIR 10 16 TRCMD 9 8 SPCMD 2 1 0 CMDNB This register is write-protected while CMDRDY is 0 in MCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD).
• MAXLAT: Max Latency for Command to Response 0: 5-cycle max latency 1: 64-cycle max latency • TRCMD: Transfer Command Value Transfer Type 0 0 No data transfer 0 1 Start data transfer 1 0 Stop data transfer 1 1 Reserved • TRDIR: Transfer Direction 0: Write 1: Read • TRTYP: Transfer Type Value Transfer Type 0 0 0 MMC/SDCard Single Block 0 0 1 MMC/SDCard Multiple Block 0 1 0 MMC Stream 0 1 1 Reserved 1 0 0 SDIO Byte 1 0 1 SDIO Block 1 1 0 Reserved 1 1 1 Reserved
39.10.7 MCI Block Register Name: MCI_BLKR Address: 0xFFF80018 (0), 0xFFF84018 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
39.10.8 MCI Response Register Name: MCI_RSPR Address: 0xFFF80020 (0), 0xFFF84020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
39.10.
39.10.
39.10.11 MCI Status Register Name: MCI_SR Address: 0xFFF80040 (0), 0xFFF84040 (1) Access: Read-only 31 30 29 28 27 26 25 24 UNRE OVRE – – – – – – 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 TXBUFE RXBUFF – – – – SDIOIRQB SDIOIRQA 7 6 5 4 3 2 1 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY • CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent.
The NOTBUSY flag allows to deal with these different states. 0: The MCI is not ready for new data transfer. Cleared at the end of the card response. 1: The MCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior.
• DCRCE: Data CRC Error 0: No error. 1: A CRC16 error has been detected in the last data block. Cleared by reading in the MCI_SR. • DTOE: Data Time-out Error 0: No error. 1: The data time-out set by DTOCYC and DTOMUL in MCI_DTOR has been exceeded. Cleared by reading in the MCI_SR. • OVRE: Overrun 0: No error. 1: At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. • UNRE: Underrun 0: No error.
39.10.
• OVRE: Overrun Interrupt Enable • UNRE: UnderRun Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
39.10.
• OVRE: Overrun Interrupt Disable • UNRE: UnderRun Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
39.10.
• OVRE: Overrun Interrupt Mask • UNRE: UnderRun Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
40. Ethernet MAC 10/100 (EMAC) 40.1 Description The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.
40.3 Block Diagram Figure 40-1.
40.4 Functional Description The MACB has several clock domains: System bus clock (AHB and APB): DMA and register blocks Transmit clock: transmit block Receive clock: receive and address checker blocks The only system constraint is 160 MHz for the system bus clock, above which MDC would toggle at above 2.5 MHz. The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps).
40.4.1.1 FIFO The FIFO depths are 28 bytes for receive and 28 bytes for transmit and area function of the system clock speed, memory latency and network speed. Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for three more. For transmit, a bus request is generated when there is space for four words, or when there is space for two words if the next transfer is to be only one or two words.
Table 40-1. Receive Buffer Descriptor Entry (Continued) Bit Function 22 Type ID match 21 VLAN tag detected (i.e., type id of 0x8100) 20 Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier) 19:17 VLAN priority (only valid if bit 21 is set) 16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set) 15 End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14.
For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero.
Transmission control is implemented with a Tx_go variable which is readable in the transmit status register at bit location 3. The Tx_go variable is reset when: ̶ transmit is disabled ̶ a buffer descriptor with its ownership bit set is read ̶ a new value is written to the transmit buffer queue pointer register ̶ bit 10, tx_halt, of the network control register is written ̶ there is a transmit error such as too many retries or a transmit underrun.
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed.
The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to 10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default.
The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: Base address + 0x98 0x87654321 (Bottom) Base address + 0x9C 0x0000CBA9 (Top) And for a successful match to the Type ID register, the following should be set up: Base address + 0xB8 0x00004321 40.4.
40.4.9 Type ID Checking The contents of the type_id register are compared against the length/type ID of received frames (i.e., bytes 13 and 14). Bit 22 in the receive buffer descriptor status is set if there is a match. The reset state of this register is zero which is unlikely to match the length/type ID of any valid Ethernet frame. Note: A type ID match does not affect whether a frame is copied to memory. 40.4.10 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 40-4. 802.
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in Table 40-5. Table 40-5.
40.5.1.2 Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in “Receive Buffer Descriptor Entry” on page 784. It points to this data structure. Figure 40-2.
40.5.1.4 Address Matching The EMAC register-pair hash address and the four specific address register-pairs must be written with the required values. Each register-pair comprises a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register-pair after the bottom-register has been written and reenabled when the top register is written. See “Address Checking Block” on page 789. for details of address matching.
40.6 Ethernet MAC 10/100 (EMAC) User Interface Table 40-6.
Table 40-6.
40.6.1 Network Control Register Name: EMAC_NCR Address: 0xFFFBC000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
• TSTART: Start transmission Writing one to this bit starts transmission. • THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
40.6.2 Network Configuration Register Name: EMAC_NCFGR Address: 0xFFFBC004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 – 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
• CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). Value MDC 00 MCK divided by 8 (MCK up to 20 MHz) 01 MCK divided by 16 (MCK up to 40 MHz) 10 MCK divided by 32 (MCK up to 80 MHz) 11 MCK divided by 64 (MCK up to 160 MHz) • RTY: Retry test Must be set to zero for normal operation.
40.6.3 Network Status Register Name: EMAC_NSR Address: 0xFFFBC008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0: The PHY logic is running. 1: The PHY management logic is idle (i.e., has completed).
40.6.4 Transmit Status Register Name: EMAC_TSR Address: 0xFFFBC014 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
40.6.5 Receive Buffer Queue Pointer Register Name: EMAC_RBQP Address: 0xFFFBC018 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
40.6.6 Transmit Buffer Queue Pointer Register Name: EMAC_TBQP Address: 0xFFFBC01C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
40.6.7 Receive Status Register Name: EMAC_RSR Address: 0xFFFBC020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
40.6.8 Interrupt Status Register Name: EMAC_ISR Address: 0xFFFBC024 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
• PTZ: Pause Time Zero Set when the pause time register, 0x38 decrements to zero. Cleared on a read.
40.6.9 Interrupt Enable Register Name: EMAC_IER Address: 0xFFFBC028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt. • RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
• PTZ: Pause Time Zero Enable pause time zero interrupt.
40.6.10 Interrupt Disable Register Name: EMAC_IDR Address: 0xFFFBC02C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt. • RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
• PTZ: Pause Time Zero Disable pause time zero interrupt.
40.6.11 Interrupt Mask Register Name: EMAC_IMR Address: 0xFFFBC030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
• PTZ: Pause Time Zero Pause time zero interrupt masked.
40.6.12 PHY Maintenance Register Name: EMAC_MAN Address: 0xFFFBC034 Access: Read/Write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 PHYA 20 REGA 19 18 17 16 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written.
40.6.13 Pause Time Register Name: EMAC_PTR Address: 0xFFFBC038 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
40.6.14 Hash Register Bottom Name: EMAC_HRB Address: 0xFFFBC090 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See “Hash Addressing” on page 790.
40.6.15 Hash Register Top Name: EMAC_HRT Address: 0xFFFBC094 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 63:32 of the hash address register. See “Hash Addressing” on page 790.
40.6.16 Specific Address 1 Bottom Register Name: EMAC_SA1B Address: 0xFFFBC098 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
40.6.17 Specific Address 1 Top Register Name: EMAC_SA1T Address: 0xFFFBC09C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
40.6.18 Specific Address 2 Bottom Register Name: EMAC_SA2B Address: 0xFFFBC0A0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
40.6.19 Specific Address 2 Top Register Name: EMAC_SA2T Address: 0xFFFBC0A4 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
40.6.20 Specific Address 3 Bottom Register Name: EMAC_SA3B Address: 0xFFFBC0A8 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
40.6.21 Specific Address 3 Top Register Name: EMAC_SA3T Address: 0xFFFBC0AC Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
40.6.22 Specific Address 4 Bottom Register Name: EMAC_SA4B Address: 0xFFFBC0B0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
40.6.23 Specific Address 4 Top Register Name: EMAC_SA4T Address: 0xFFFBC0B4 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
40.6.24 Type ID Checking Register Name: EMAC_TID Address: 0xFFFBC0B8 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID checking For use in comparisons with received frames TypeID/Length field.
40.6.25 User Input/Output Register Name: EMAC_USRIO Address: 0xFFFBC0C0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CLKEN 0 RMII • RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. • CLKEN When set, this bit enables the transceiver input clock.
40.6.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers.
40.6.26.1 Pause Frames Received Register Name: EMAC_PFR Address: 0xFFFBC03C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 FROK 7 6 5 4 FROK • FROK: Pause Frames received OK A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
40.6.26.2 Frames Transmitted OK Register Name: EMAC_FTO Address: 0xFFFBC040 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FTOK 15 14 13 12 FTOK 7 6 5 4 FTOK • FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
40.6.26.3 Single Collision Frames Register Name: EMAC_SCF Address: 0xFFFBC044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun.
40.6.26.4 Multicollision Frames Register Name: EMAC_MCF Address: 0xFFFBC048 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 MCF 7 6 5 4 MCF • MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
40.6.26.5 Frames Received OK Register Name: EMAC_FRO Address: 0xFFFBC04C Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
40.6.26.6 Frames Check Sequence Errors Register Name: EMAC_FCSE Address: 0xFFFBC050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 FCSE • FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register).
40.6.26.
40.6.26.8 Deferred Transmission Frames Register Name: EMAC_DTF Address: 0xFFFBC058 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 DTF 7 6 5 4 DTF • DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission.
40.6.26.9 Late Collisions Register Name: EMAC_LCOL Address: 0xFFFBC05C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
40.6.26.10 Excessive Collisions Register Name: EMAC_ECOL Address: 0xFFFBC060 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 EXCOL • EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
40.6.26.11 Transmit Underrun Errors Register Name: EMAC_TUND Address: 0xFFFBC064 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
40.6.26.
40.6.26.13 Receive Resource Errors Register Name: EMAC_RRE Address: 0xFFFBC06C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.
40.6.26.14 Receive Overrun Errors Register Name: EMAC_ROV Address: 0xFFFBC070 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 ROVR • ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.
40.6.26.15 Receive Symbol Errors Register Name: EMAC_RSE Address: 0xFFFBC074 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
40.6.26.
40.6.26.17 Receive Jabbers Register Name: EMAC_RJA Address: 0xFFFBC07C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.
40.6.26.18 Undersize Frames Register Name: EMAC_USF Address: 0xFFFBC080 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 USF • USF: Undersize frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
40.6.26.19 SQE Test Errors Register Name: EMAC_STE Address: 0xFFFBC084 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode.
40.6.26.20 Received Length Field Mismatch Register Name: EMAC_RLE Address: 0xFFFBC088 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RLFM • RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field.
41. USB Host Port (UHP) 41.1 Description The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.
Access to the USB host operational registers is achieved through the AHB bus slave interface.
41.5 Functional Description Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 41.5.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers.
41.5.2 Host Controller Driver Figure 41-3. USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: 41.6 Host controller hardware and serial engine: Transmits and receives USB data on the bus. Host controller driver: Drives the Host controller hardware and handles the USB protocol.
42. USB Device Port (UDP) 42.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode.
42.4 Typical Connection Figure 42-2. Board Schematic to Interface Device Peripheral 5V Bus Monitoring PIO 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 330 K 330 K 42.4.1 USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows: the application detects all device states as defined in chapter 9 of the USB specification; to reduce power consumption the host is disconnected for line termination.
42.5 Functional Description 42.5.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 42-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
42.5.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 42-3.
42.5.2 Handling Transactions with USB V2.0 Device Peripheral 42.5.2.1 Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments.
42.5.2.3 Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx. 3.
Figure 42-7.
Figure 42-8.
Figure 42-9.
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4.
RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 42.5.2.8 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) A functional stall is used when the halt feature associated with the endpoint is set.
42.5.2.9 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 42-1 “USB Endpoint Description”. 42.5.2.10 Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.
42.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 42-14.
42.5.3.2 Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 KΩ pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 KΩ resistor to 3.3V and DM is pulled down by the 15 KΩ resistor of the host. To enable integrated pullup, the PUON bit in the UDP_TXVC register must be set.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 42.5.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed).
42.6 USB Device Port (UDP) User Interface Warning: Table 42-4. The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register.
42.6.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0xFFF78000 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
42.6.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0xFFF78004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 – 3 – 2 – 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0: Device is not in address state.
42.6.3 UDP Function Address Register Name: UDP_FADDR Address: 0xFFF78008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
42.6.
42.6.
42.6.
• WAKEUP: USB Bus WAKEUP Interrupt 0: USB Bus Wakeup Interrupt is disabled. 1: USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.
42.6.
• RXRSM: UDP Resume Interrupt Status 0: No UDP Resume Interrupt pending. 1: UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR. • SOFINT: Start of Frame Interrupt Status 0: No Start of Frame Interrupt pending. 1: Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected.
42.6.8 UDP Interrupt Clear Register Name: UDP_ICR Address: 0xFFF78020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 – 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0: No effect. 1: Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0: No effect. 1: Clears UDP Resume Interrupt.
42.6.
42.6.10 UDP Endpoint Control and Status Register Name: UDP_CSRx [x = 0..
• RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0: Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO's Bank 0. 1: A data packet has been received, it has been stored in the FIFO's Bank 0.
ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0: No error in the previous isochronous transfer. 1: CRC error has been detected, data available in the FIFO are corrupted. Write: 0: Resets the ISOERROR flag, clears the interrupt. 1: No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0: There is no data to send. 1: The data is waiting to be sent upon reception of token IN.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0: Notifies USB device that data have been read in the FIFO’s Bank 1. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO's Bank 1. 1: A data packet has been received, it has been stored in FIFO's Bank 1.
• EPEDS: Endpoint Enable Disable Read: 0: Endpoint disabled. 1: Endpoint enabled. Write: 0: Disables endpoint. 1: Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller.
42.6.11 UDP FIFO Data Register Name: UDP_FDRx [x = 0..5] Address: 0xFFF7804C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx is the number of bytes to be read from the FIFO (sent by the host).
42.6.12 UDP Transceiver Control Register Name: UDP_TXVC Address: 0xFFF78074 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – Warning: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
43. LCD Controller (LCDC) 43.1 Overview The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method.
Block Diagram Figure 43-1. LCD Macrocell Block Diagram AHB SLAVE AHB MASTER SPLIT DMA Controller AHB IF CFG AHB SLAVE DMA Data Dvalid Dvalid CH-U CTRL CH-L Lower Push Upper Push Input Interface FIFO LCD Controller Core Configuration IF CFG AHB SLAVE SERIALIZER DATAPATH 43.
43.3 I/O Lines Description Table 43-1. I/O Lines Description Name Description Type LCDCC Contrast control signal Output LCDHSYNC Line synchronous signal (STN) or Horizontal synchronous signal (TFT) Output LCDDOTCK LCD clock signal (STN/TFT) Output LCDVSYNC Frame synchronous signal (STN) or Vertical synchronization signal (TFT) Output LCDDEN Data enable signal Output LCDD[23:0] LCD Data Bus output Output 43.4 Product Dependencies 43.4.
43.5.1.3 Channel-U This block stores the base address and the number of words transferred for this channel (frame in single scan mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame signal. It has two pointers, the base address and the number of words to transfer. When the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel.
Figure 43-2. Datapath Structure Input Interface FIFO Serializer Configuration IF Palette Control Interface Dithering Output Shifter Output Interface This module transforms the data read from the memory into a format according to the LCD module used. It has four different interfaces: the input interface, the output interface, the configuration interface and the control interface. The input interface connects the datapath with the DMA controller.
These parameters are different for the different configurations of the LCD Controller and are shown in Table 43-2. Table 43-2. Datapath Parameters Configuration DISTYPE SCAN IFWIDTH initial_latency cycles_per_data 9 1 TFT STN Mono Single 4 13 4 STN Mono Single 8 17 8 STN Mono Dual 8 17 8 STN Mono Dual 16 25 16 STN Color Single 4 11 2 STN Color Single 8 12 3 STN Color Dual 8 14 4 STN Color Dual 16 15 6 43.5.2.
Table 43-4.
Table 43-6.
For the structure of each LUT entry, see Table 43-8. Table 43-8. Lookup Table Structure in the Memory Address Data Output [15:0] 00 Intensity_bit_0 Blue_value_0[4:0] Green_value_0[4:0] Red_value_0[4:0] 01 Intensity_bit_1 Blue_value_1[4:0] Green_value_1[4:0] Red_value_1[4:0] FE Intensity_bit_254 Blue_value_254[4:0] Green_value_254[4:0] Red_value_254[4:0] FF Intensity_bit_255 Blue_value_255[4:0] Green_value_255[4:0] Red_value_255[4:0] ...
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively. The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The dithering pattern for the first pair member is the inversion of the one for the second. The DP_i registers contain a series of 4-bit patterns. The (3-m)th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame.
Table 43-11.
Table 43-12. Minimum LCDDOTCK Period in LCDC Core Clock Cycles Configuration DISTYPE SCAN IFWIDTH LCDDOTCK Period TFT 1 STN Mono Single 4 4 STN Mono Single 8 8 STN Mono Dual 8 8 STN Mono Dual 16 16 STN Color Single 4 2 STN Color Single 8 2 STN Color Dual 8 4 STN Color Dual 16 6 The LCDDEN signal indicates valid data in the LCD Interface.
Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register. The pulse width is equal to (VPW+1) lines. Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in STN Mode. Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of LCDTIM2 register.
Figure 43-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1 Frame Period (VPW+1) Lines LCDVSYNC Vertical Fron t Porch = VFP Lines Vertical Back Porch = VBP Lines VHDLY+1 LCDHSYNC LCDDEN LCDDOTCK LCDD Line Period VHDLY+1 HPW+1 HOZVAL+1 HBP+1 HFP+2 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK Figure 43-5.
In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. In color mode, Horizontal_display_size equals three times the number of horizontal pixels.
For PWM mode, the frequency of the counter can be adjusted to four different values using field PS of CONTRAST_CTR register. 43.5.3 LCD Interface The LCD Controller interfaces with the LCD Module through the LCD Interface (Table 43-13 on page 907). The Controller supports the following interface configurations: 24-bit TFT single scan, 16-bit STN Dual Scan Mono (Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit single scan Mono (Color).
Figure 43-7. Single Scan Monochrome and Color 4-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] P0 P4 LCDD [2] P1 P5 LCDD [1] P2 P6 LCDD [0] P3 P7 LCDD [3] R0 G1 LCDD [2] G0 B1 LCDD [1] B0 R2 LCDD [0] R1 G2 LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK Figure 43-8.
Figure 43-9.
Figure 43-10.
Table 43-13.
43.6 Interrupts The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are: DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer. FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty. FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is full.
̶ LCDFRMCFG register: program the dimensions of the LCD module used. ̶ LCDFIFO register: To program it, use the formula in “FIFO” on page 893. ̶ DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules. They are loaded with recommended patterns at reset, so it is not necessary to write anything on them.
43.9 2D Memory Addressing The LCDC can be configured to work on a frame buffer larger than the actual screen size. By changing the values in a few registers, it is easy to move the displayed area along the frame buffer width and height. Figure 43-11.
43.10 Register Configuration Guide Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. 43.10.1 STN Mode Example STN color(R,G,B) 320 * 240, 8-bit single scan, 70 frames/sec, Master clock = 60 MHz Data rate: 320 * 240 * 70 * 3/8 = 2.016 MHz HOZVAL = ((3 * 320)/8) - 1 LINEVAL = 240 -1 CLKVAL = (60 MHz/ (2 * 2.
43.11 LCD Controller (LCDC) User Interface Table 43-14.
Table 43-14.
43.11.1 DMA Base Address Register 1 Name: DMABADDR1 Address: 0x00700000 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 BADDR-U 23 22 21 20 BADDR-U 15 14 13 12 BADDR-U 7 6 5 4 BADDR-U • BADDR-U Base Address for the upper panel in dual scan mode. Base Address for the complete frame in single scan mode.
43.11.2 DMA Base Address Register 2 Name: DMABADDR2 Address: 0x00700004 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BADDR-L 23 22 21 20 BADDR-L 15 14 13 12 BADDR-L 7 6 5 4 BADDR-L • BADDR-L Base Address for the lower panel in dual scan mode only.
43.11.3 DMA Frame Pointer Register 1 Name: DMAFRMPT1 Address: 0x00700008 Access: Read-only 31 – 23 – 15 30 – 22 29 – 21 14 13 7 6 5 28 – 20 27 – 19 FRMPT-U 12 11 FRMPT-U 4 3 FRMPT-U 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-U Current value of frame pointer for the upper panel in dual scan mode. Current value of frame pointer for the complete frame in single scan mode. Down count from FRMSIZE to 0.
43.11.4 DMA Frame Pointer Register 2 Name: DMAFRMPT2 Address: 0x0070000C Access: Read-only 31 – 23 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 5 4 27 – 19 FRMPT-L 11 FRMPT-L 3 FRMPT-L 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-L Current value of frame pointer for the Lower panel in dual scan mode only. Down count from FRMSIZE to 0. Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame).
43.11.5 DMA Frame Address Register 1 Name: DMAFRMADD1 Address: 0x00700010 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-U 23 22 21 20 FRMADD-U 15 14 13 12 FRMADD-U 7 6 5 4 FRMADD-U • FRMADD-U Current value of frame address for the upper panel in dual scan mode. Current value of frame address for the complete frame in single scan.
43.11.6 DMA Frame Address Register 2 Name: DMAFRMADD2 Address: 0x00700014 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-L 23 22 21 20 FRMADD-L 15 14 13 12 FRMADD-L 7 6 5 4 FRMADD-L • FRMADD-L Current value of frame address for the lower panel in single scan mode only. Note: This register is read-only and contains the current value of the last DMA transaction in the bus for the panel.
43.11.7 DMA Frame Configuration Register Name: DMAFRMCFG Address: 0x00700018 Access: Read/Write 31 – 23 – 15 30 29 28 22 21 20 14 13 12 7 6 5 4 27 BRSTLN 19 FRMSIZE 11 FRMSIZE 3 FRMSIZE 26 25 24 18 17 16 10 9 8 2 1 0 • FRMSIZE: Frame Size In single scan mode, this is the frame size in words. In dual scan mode, this is the size of each panel.
43.11.8 DMA Control Register Name: DMACON Address: 0x0070001C Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 DMA2DEN 27 – 19 – 11 – 3 DMAUPDT 26 – 18 – 10 – 2 DMABUSY 25 – 17 – 9 – 1 DMARST 24 – 16 – 8 – 0 DMAEN • DMAEN: DMA Enable 0: DMA is disabled. 1: DMA is enabled. • DMARST: DMA Reset (Write-only) 0: No effect. 1: Reset DMA module. DMA Module should be reset only when disabled and in idle state. • DMABUSY: DMA Busy 0: DMA module is idle.
43.11.9 LCD DMA 2D Addressing Register Name: DMA2DCFG Address: 0x00700020 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 27 25 24 19 – 11 26 PIXELOFF 18 – 10 20 – 12 17 – 9 16 – 8 7 6 5 4 3 2 1 0 ADDRINC ADDRINC • ADDRINC: DMA 2D Addressing Address increment When 2D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the number of bytes that the DMA controller must jump between screen lines.
43.11.10 LCD Control Register 1 Name: LCDCON1 Address: 0x00700800 Access: Read/Write, except LINECNT: Read-only 31 30 29 28 27 26 25 24 18 CLKVAL 10 – 2 – 17 16 9 – 1 – 8 – 0 BYPASS LINECNT 23 15 7 – 22 LINECNT 14 CLKVAL 6 – 21 20 19 13 12 5 – 4 – 11 – 3 – • BYPASS: Bypass LCDDOTCK divider 0: The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1: The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.
43.11.
• INVVD: LCDD polarity 0: Normal 1: Inverted • INVFRAME: LCDVSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVLINE: LCDHSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVCLK: LCDDOTCK polarity 0: Normal (LCDD fetched at LCDDOTCK falling edge) 1: Inverted (LCDD fetched at LCDDOTCK rising edge) • INVDVAL: LCDDEN polarity 0: Normal (active high) 1: Inverted (active low) • CLKMOD: LCDDOTCK mode 0: LCDDOTCK only active during active display period 1: LCDDOTCK always active •
43.11.12 LCD Timing Configuration Register 1 Name: LCDTIM1 Address: 0x00700808 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 28 – 20 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VHDLY 19 VPW 13 12 VBP 7 6 5 4 VFP • VFP: Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0. • VBP: Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
43.11.13 LCD Timing Configuration Register 2 Name: LCDTIM2 Address: 0x0070080C Access: Read/Write 31 30 29 28 27 26 25 24 13 20 – 12 19 – 11 18 – 10 17 – 9 16 – 8 5 4 3 2 1 0 HFP 23 15 – 7 22 HFP 14 – 6 21 HPW HBP • HBP: Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is (HBP+1) LCDDOTCK cycles. • HPW: Horizontal synchronization pulse width Width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is (HPW+1) LCDDOTCK cycles.
43.11.
43.11.15 LCD FIFO Register Name: LCDFIFO Address: 0x00700814 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 FIFOTH FIFOTH • FIFOTH: FIFO Threshold Must be programmed with: FIFOTH = 2048 - (2 x DMA_BURST_LENGTH + 3) where: • 2048 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode.
43.11.
43.11.
43.11.
43.11.
43.11.
43.11.
43.11.
43.11.
43.11.24 Power Control Register Name: PWRCON Address: 0x0070083C Access: Read/Write 31 LCD_BUSY 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 GUARD_TIME 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 LCD_PWR • LCD_PWR: LCD module power control 0 = lcd_pwr signal is low, other lcd_* signals are low. 0->1 = lcd_* signals activated, lcd_pwr is set high with the delay of GUARD_TIME frame periods. 1 = lcd_pwr signal is high, other lcd_* signals are active.
43.11.25 Contrast Control Register Name: CONTRAST_CTR Address: 0x00700840 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ENA 26 – 18 – 10 – 2 POL 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PS • PS This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows: PS 0 0 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK. 0 1 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/2.
43.11.26 Contrast Value Register Name: CONTRAST_VAL Address: 0x00700844 Access: Read/Write 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 CVAL • CVAL PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
43.11.
43.11.
43.11.
43.11.
43.11.
43.11.
43.11.
44. Two D Graphics Controller (TDGC) 44.1 Description The Two D Graphics Controller (TDGC) features a hardware accelerator which highly simplifies drawing tasks and graphic management operations. The hardware accelerator makes it easy to draw lines and complex polygons and to perform block transfers within the frame buffer. The TDGC also features a draw command queue that automatically executes a more complex drawing function that is composed of several register accesses.
44.2 Block Diagram Figure 44-1.
44.3 Functional Description 44.3.1 Hardware Acceleration The hardware acceleration performs multiple block transfers, line draw or fill commands by issuing draw commands to the controller. This technique makes it possible to get rid of complex software layers. 44.3.1.1 Line Draw Lines can be drawn up to a specific width scalable from 1 to 16 pixels. They can also be drawn as a broken line with a pattern set by a 16-bit pattern register.
44.3.1.2 Line Draw Modes Absolute Line Draw First pixel position on the line is the pixel position loaded into source/begin x and source/begin y registers. Last pixel position on the line is the pixel position loaded into target/end x and target/end y registers. Figure 44-2. Absolute Line Draw From (2,0) to (5,0) (0,0) X 2,0 3,0 4,0 (9,0) 5,0 Y DISPLAY (0,4) (9,4) Relative Line Draw First pixel position on the line is the pixel position loaded into source/begin x and source/begin y registers.
44.3.1.3 Relative Line Draw with Update XY Option First pixel position is loaded into source/begin x and source/begin y registers and last pixel position is loaded into target/end x target/end y registers. After the necessary color and pattern are loaded into appropriate registers, respectively TDGC_CSR and TDGC_LPR, line draw is initiated with a write to TR register. If the line needs to be extended, then a single write to the TDGC_GOR with update XY option set initiates line draw (extension).
44.3.1.5 2D Line Draw with Broken Pattern 0xEBBB In 2D line drawing, the bit pattern does not rotate. Each pixel rendered is based on the last two bits of its X and Y addresses as shown below. Table 44-1. 2D Line Draw Pattern X[1:0] = 0 X[1:0] = 1 X[1:0] = 2 X[1:0] = 3 Y[1:0] = 0 LPT[12] LPT[13] LPT[14] LPT[15] Y[1:0] = 1 LPT[8] LPT[9] LPT[10] LPT[11] Y[1:0] = 2 LPT[4] LPT[5] LPT[6] LPT[7] Y[1:0] = 3 LPT[0] LPT[1] LPT[2] LPT[3] Figure 44-6.
44.3.1.6 Block Transfer A rectangle (or square) shape in pixel units can be transferred between areas in the virtual memory area of the VRAM. Logical operations such as AND, OR, XOR, NOT, NOR, NAND and XNOR can be made between the pixels in the source area and the destination area and stored in the destination area. The following registers need to be programmed to perform a block transfer: TDGC_BTSXR: size in pixel units on X-axis. TDGC_BTSYR: size in pixel units on Y-axis.
44.3.1.8 Relative Block Transfer A block of data is copied (or xor/or/and/xnor/nand/not/nor/xnor) from the start position loaded into start x and start y registers to a position offset based on the target position loaded into target x and target y registers with respect to start position. The size of data is based on size x and size y registers. Figure 44-8. Relative Block Transfer From (1,0) to (4,4) Size (4,2) X (0,0) 1,0 1,1 2,0 (11,0) 4,0 3,1 Y 5,4 5,5 6,4 8,4 7,5 DISPLAY (0,8) (11,8) 44.3.
44.3.1.10 Clipping This function disables drawing outside the selected rectangular field. The clipping x and y coordinates are defined by the values, in pixel units, programmed in four clipping vertex registers TDGC_CXMINR, TDGC_CXMAXR, TDGC_CYMINR, TDGC_CYMAXR. Clipping is enabled by setting CEN bitfield in TDGC_CCR. Figure 44-10.
44.3.1.11 Draw Command Queuing Multiple block transfer, line draw or fill commands can be issued to the TDGC by writing the commands to a 64 x 16-bit wide FIFO. All drawing specific registers can be written via writes to the FIFO by writing the address, length and the register value to the command queue. Length is based on the number of consecutive register writes. All accesses to the command queue FIFO are by reading/writing to the 16-bit wide TDGC_CQR.
44.3.1.12 Recommended Procedure for Using the Command Queue Load the entire queue (equal to 64) with commands. Enable command queue buffer empty interrupt (BUFE) in TDGC_GMR if using interrupts instead of polling. Wait for Command queue buffer empty status (BUFE) in TDGC_GIR with a five second timeout or wait for an interrupt event if interrupt is enabled (recommended).
44.4 Examples of Drawing Functions 44.4.1 Line Draw This function draws a thick (2 pixels wide) solid black line from start point (startx, starty) to end point (endx, endy). startx, starty, endx, endy should be in pixel units. Void line_draw(unsigned short startx, unsigned short starty, unsigned short endx, unsigned short endy) { while(graphics_control.TDGC_GSR & 3); graphics_control.TDGC_SBXR = startx; graphics_control.TDGC_SBYR = starty; graphics_control.TDGC_TEXR = endx; graphics_control.
graphics_control.TDGC_TEXR = endx; graphics_control.TDGC_TEYR = endy; graphics_control.TDGC_LOR = 0x00; // Select logic operation MOV graphics_control.TDGC_CSR = 0x00; // Colour black graphics_control.TDGC_LWR = 0x02; // 2 pixels wide graphics_control.TDGC_LPR = 0x5555; // Patterned line ON, OFF, ON, OFF … // set clip rectangle boundary (4,2), (8,2), (4,4), (8,4) graphics_control.TDGC_CXMINR = 4; graphics_control.TDGC_CXMAXR = 8; graphics_control.TDGC_CYMINR = 2; graphics_control.
{ // Get BUFW_CNTR from TDGC_CQCR and see if there is enough room in FIFO if((((graphics_control.TDGC_CQCR & 0xFC0) >> 6) + add_cnt) >= 64) { if(interrupt_enabled) // Wait for buffer empty interrupt to rise which should be enabled at first place in TDGC_GIMR. sleep_until_event_from_isr; else while(!graphics_control.
44.5 Two D Graphic Controller (TDGC) User Interface Table 44-2.
Table 44-2.
44.5.1 Block Transfer Size X Register Name: TDGC_BTSXR Address: 0xFFFC8000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 XSIZE 8 7 6 5 4 3 2 1 0 XSIZE • XSIZE Sets size X of a bit block transfer in pixel units.
44.5.2 Block Transfer Size Y Register Name: TDGC_BTSYR Address: 0xFFFC8004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 YSIZE 8 7 6 5 4 3 2 1 0 YSIZE • YSIZE Sets size Y of a bit block transfer in pixel units.
44.5.3 Source/Begin X Register Name: TDGC_SBXR Address: 0xFFFC8008 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSRC 23 22 21 20 XSRC 15 14 13 12 XSRC 7 6 5 4 XSRC • XSRC XSRC[10–0]: Sets source X of a bit block transfer/begin point X of line draw in pixel units. XSRC[31–0]: Sets begin point X of clipped line draw in pixel units.
44.5.4 Source/Begin Y Register Name: TDGC_SBYR Address: 0xFFFC800C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 YSRC 23 22 21 20 YSRC 15 14 13 12 YSRC 7 6 5 4 YSRC • YSRC YSRC[10–0]: Sets source Y of a bit block transfer/begin point Y of line draw in pixel units. YSRC[31–0]: Sets begin point Y of clipped line draw in pixel units.
44.5.5 Target/End X Register Name: TDGC_TEXR Address: 0xFFFC8010 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XEND 23 22 21 20 XEND 15 14 13 12 XEND 7 6 5 4 XEND • XEND XEND[10–0]: Sets source Y of a bit block transfer/begin point Y of line draw in pixel units. XEND[31–0]: Sets begin point Y of clipped line draw in pixel units.
44.5.6 Target/End Y Register Name: TDGC_TEYR Address: 0xFFFC8014 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 YEND 23 22 21 20 YEND 15 14 13 12 YEND 7 6 5 4 YEND • YEND YEND[10–0]: Sets source Y of a bit block transfer/begin point Y of line draw in pixel units. YEND[31–0]: Sets begin point Y of clipped line draw in pixel units.
44.5.7 Line Width Register Name: TDGC_LWR Address: 0xFFFC8018 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 • LWD Line width in pixel units.
44.5.8 Line Pattern Register Name: TDGC_LPR Address: 0xFFFC801C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 LPT 7 6 5 4 LPT • LPT: Line Pattern Sets 16-bit 1D pattern or 4 x 4-bit 2D pattern for line drawing. In 1D pattern drawing, LPT[0] is the starting point of the pattern. After each operation, LPT will rotate one bit to the right.
44.5.9 Color Select Register Name: TDGC_CSR Address: 0xFFFC8020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CLR 15 14 13 12 CLR 7 6 5 4 CLR • CLR: Color At 1 bpp only CLR[3] is active. 0: White is selected. 1: Black is selected. At 2 bpp only CLR[3:2] is active. Values Color 00 White 01 Light Grey 10 Dark Grey 11 Black At 4 bpp, only CLR[3:0] is active.
44.5.
44.5.11 Graphics Operation Register Name: TDGC_GOR Address: 0xFFFC8028 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 OP3 2 OP2 1 OP1 0 OP0 GOC • GOC: Graphic Operation Code GOC Function 0000 No Operation 1101 Line Drawing 1011 Block Transfer • OPx: Option There are four options, each one allows each operation code to behave as shown below.
The table below gives the possible operation depending on command code = (TDGC_LOR) | (TDGC_GOR << 8) Command Code[15:0] Function 0x00 No Operation 0xB00 Block Transfer, Relative, No Update, MOV 0xB10 Block Transfer, Relative, Update Y, MOV 0xB20 Block Transfer, Relative, Update X, MOV 0xB40 Block Transfer, Absolute, No Update, MOV 0xB50 Block Transfer, Absolute, Update Y, MOV 0xB60 Block Transfer, Absolute, Update X, MOV 0xB01 Block Transfer, Relative, No Update, OR 0xB11 Block Transfer,
44.5.12 Extended Begin X Register Name: TDGC_EBXR Address: 0xFFFC802C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 EXT_BX 7 6 5 4 EXT_BX • EXT_BX Sets begin point x (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing.
44.5.13 Extended Begin Y Register Name: TDGC_EBYR Address: 0xFFFC8030 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 EXT_BY 7 6 5 4 EXT_BY • EXT_BY Sets begin point y (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing.
44.5.14 Extended End X Register Name: TDGC_EEXR Address: 0xFFFC8034 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 EXT_EX 7 6 5 4 EXT_EX • EXT_EX Sets end point x (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:16] is written to a separate register.
44.5.15 Extended End Y Register Name: TDGC_EEYR Address: 0xFFFC8038 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 EXT_EY 7 6 5 4 EXT_EY • EXT_EY Sets end point y (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:16] is written to a separate register.
44.5.16 Extended Color Select Register Name: TDGC_ECSR Address: 0xFFFC803C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 EXT_CSR • EXT_CSR Sets MSB[23:16] of color selection for 24 bpp. This register is only used when in 24 bpp mode and when command queue is used for drawing.
44.5.17 Clip Control Register Name: TDGC_CCR Address: 0xFFFC8040 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CEN • CEN 1: Enable clipping. 0: Disable clipping.
44.5.18 Clip Rectangle Minimum X Register Name: TDGC_CXMINR Address: 0xFFFC8044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 CXMIN 8 7 6 5 4 3 2 1 0 CXMIN • CXMIN Minimum x-coordinate boundary of the clip rectangle.
44.5.19 Clip Rectangle Maximum X Register Name: TDGC_CXMAXR Address: 0xFFFC8048 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 CXMAX 8 7 6 5 4 3 2 1 0 CXMAX • CXMAX Maximum x-coordinate boundary of the clip rectangle.
44.5.20 Clip Rectangle Minimum Y Register Name: TDGC_CYMINR Address: 0xFFFC804C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 CYMIN 8 7 6 5 4 3 2 1 0 CYMIN • CYMIN Minimum y-coordinate boundary of the clip rectangle.
44.5.21 Clip Rectangle Maximum Y Register Name: TDGC_CYMAXR Address: 0xFFFC8050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 CYMAX 8 7 6 5 4 3 2 1 0 CYMAX • CYMAX Maximum y-coordinate boundary of the clip rectangle.
44.5.22 Graphics Status Register Name: TDGC_GSR Address: 0xFFFC8054 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 BTB 0 LTB • LTB 1: Line drawing engine is busy. 0: Line drawing engine is available. • BTB 1: Block transfer engine busy. 0: Block transfer engine available.
44.5.
44.5.24 Graphics Interrupt Register Name: TDGC_GIR Address: 0xFFFC8064 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 • BUFE: Command queue buffer empty interrupt 1: Signals buffer empty. Writing a 1 to this bit clears the interrupt.
44.5.25 Graphics Interrupt Mask Register Name: TDGC_GIMR Address: 0xFFFC8068 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 BUFE • BUFE: Command queue buffer empty interrupt enable 1: Enable command queue buffer empty interrupt. 0: Disable command queue buffer empty interrupt.
44.5.
44.5.27 Command Queue Count Register Name: TDGC_CQCR Address: 0xFFFC8078 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 6 5 4 3 1 0 7 BUFW_CNTR BUFW_CNTR 2 BUFR_CNTR • BUFR_CNTR Number of half words read from the FIFO by internal logic. • BUFW_CNTR Number of half words written to the FIFO by CPU.
44.5.28 Command Queue Status Register Name: TDGC_CQSR Address: 0xFFFC807C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 • BE: Buffer Empty 1: Buffer is empty. 0: Buffer is not empty.
44.5.29 Command Queue Register Name: TDGC_CQR Address: 0xFFFC8080 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 Q_DATA 7 6 5 4 Q_DATA • Q_DATA All data to be stored in the queue is written to this register.
44.5.30 VRAM OFFSET Register Name: TDGC_VOR Address: 0xFFFC8200 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 S8 16 PK 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 OFFSET 3 2 OFFSET • OFFSET .Offset into the VRAM which gives the first pixel position in the memory. • PK: Packed Mode 1: Selects the packed 24 bpp mode. • S8 1: Allows the use of 320 pixel offset for rows (y).
44.5.31 DATA Format Register Name: TDGC_DFR Address: 0xFFFC8204 Access: Read/Write 31 ENDIAN 30 WINCE 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • ENDIAN: ENDIANESS 1: DATA format is little endian. 0: DATA format is big endian. • WINCE 1: DATA format is WINCE compliant. 0: DATA format is not WINCE compliant.
45. Image Sensor Interface (ISI) 45.1 Overview The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller.
Block Diagram Hsync/Len Vsync/Fen Image Sensor Interface Block Diagram Timing Signals Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5 CMOS sensor pixel clock input 45.3 Config Registers Camera Interrupt Controller Camera Interrupt Request Line From Rx buffers Pixel Clock Domain APB Interface APB bus Figure 45-2.
45.3.1 Data Timing The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are shown in Figure 45-3 and Figure 45-4. In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the control register. The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface.
Table 45-3.
45.3.4 Preview Path 45.3.4.1 Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. Table 45-6. Decimation Factor Dec value 0->15 16 17 18 19 ... 124 125 126 127 Dec Factor X 1 1.063 1.
Figure 45-5. Resize Examples 32/16 decimation 1280 640 1024 480 56/16 decimation 1280 352 1024 288 45.3.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y – Y off R G = C 0 – C 2 – C 3 × C b – C boff B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB: R = 1.
45.3.4.4 FIFO and DMA Features Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation.
Figure 45-6. Three Frame Buffers Application and Memory Mapping Codec Done Codec Request frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config Space 4:2:2 Image Full ROI 45.3.5 Codec Path 45.3.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module.
45.4 Image Sensor Interface (ISI) User Interface Table 45-9.
45.4.1 ISI Control 1 Register Name: ISI_CR1 Address: 0xFFFC4000 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 CODEC_ON 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 – 10 9 FRATE 8 5 – 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 ISI_DIS 0 ISI_RST THMASK • ISI_RST: Image sensor interface reset Write-only. Refer to bit SOFTRST in Section 45.4.3 “ISI Status Register” on page 1009 for soft reset status. 0: No action 1: Resets the image sensor interface.
• FRATE: Frame rate [0..7] 0: All the frames are captured, else one frame every FRATE+1 is captured. • FULL: Full mode is allowed 1: Both codec and preview datapaths are working simultaneously • THMASK: Threshold mask 0: 4, 8 and 16 AHB bursts are allowed 1: 8 and 16 AHB bursts are allowed 2: Only 16 AHB bursts are allowed • CODEC_ON: Enable the codec path enable bit Write-only. 0: The codec path is disabled 1: The codec path is enabled and the next frame is captured.
45.4.2 ISI Control 2 Register Name: ISI_CR2 Address: 0xFFFC4004 Access: Read/Write 31 30 29 RGB_CFG 23 28 27 – 26 25 IM_HSIZE 24 20 19 18 17 16 YCC_SWAP 22 21 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE • IM_VSIZE: Vertical size of the Image sensor [0..
• YCC_SWAP: Defines the YCC image data YCC_SWAP Byte 0 Byte 1 Byte 2 Byte 3 00: Default Cb(i) Y(i) Cr(i) Y(i+1) 01: Mode1 Cr(i) Y(i) Cb(i) Y(i+1) 10: Mode2 Y(i) Cb(i) Y(i+1) Cr(i) 11: Mode3 Y(i) Cr(i) Y(i+1) Cb(i) • RGB_CFG: Defines RGB pattern when RGB_MODE is set to 1 RGB_CFG Byte 0 Byte 1 Byte 2 Byte 3 00: Default R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B 01: Mode1 B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R 10: Mode2 G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) 11: Mode3 G(LSB)/B
45.4.3 ISI Status Register Name: ISI_SR Address: 0xFFFC4008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 CDC_PND 2 SOFTRST 1 DIS 0 SOF • SOF: Start of frame 0: No start of frame has been detected. 1: A start of frame has been detected. • DIS: Image Sensor Interface disable 0: The image sensor interface is enabled.
• FO_P_OVF: FIFO preview overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. • FO_P_EMP 0:The DMA has not finished transferring all the contents of the preview FIFO. 1:The DMA has finished transferring all the contents of the preview FIFO. • FO_C_EMP 0: The DMA has not finished transferring all the contents of the codec FIFO.
45.4.4 Interrupt Enable Register Name: ISI_IER Address: 0xFFFC400C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 – 2 SOFTRST 1 DIS 0 SOF • SOF: Start of Frame 1: Enables the Start of Frame interrupt. • DIS: Image Sensor Interface disable 1: Enables the DIS interrupt.
45.4.5 ISI Interrupt Disable Register Name: ISI_IDR Address: 0xFFFC4010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 – 2 SOFTRST 1 DIS 0 SOF • SOF: Start of Frame 1: Disables the Start of Frame interrupt. • DIS: Image Sensor Interface disable 1: Disables the DIS interrupt.
45.4.6 ISI Interrupt Mask Register Name: ISI_IMR Address: 0xFFFC4014 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 – 2 SOFTRST 1 DIS 0 SOF • SOF: Start of Frame 0: The Start of Frame interrupt is disabled. 1: The Start of Frame interrupt is enabled. • DIS: Image sensor interface disable 0: The DIS interrupt is disabled.
• FO_C_EMP 0: The codec FIFO empty interrupt is disabled. 1: The codec FIFO empty interrupt is enabled. • FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled.
45.4.7 ISI Preview Register Name: ISI_PSIZE Address: 0xFFFC4020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 23 22 21 20 19 18 17 11 – 10 – 9 3 2 1 24 PREV_HSIZE 16 PREV_HSIZE 15 – 14 – 13 – 12 – 7 6 5 4 8 PREV_VSIZE 0 PREV_VSIZE • PREV_VSIZE: Vertical size for the preview path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode). • PREV_HSIZE: Horizontal size for the preview path Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).
45.4.8 ISI Preview Decimation Factor Register Name: ISI_PDECF Address: 0xFFFC4024 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 DEC_FACTOR • DEC_FACTOR: Decimation factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation.
45.4.9 ISI Preview Primary FBD Register Name: ISI_PPFBD Address: 0xFFFC4028 Access: Read/Write 31 30 29 28 27 PREV_FBD_ADDR 26 25 24 23 22 21 20 19 PREV_FBD_ADDR 18 17 16 15 14 13 12 11 PREV_FBD_ADDR 10 9 8 7 6 5 4 3 PREV_FBD_ADDR 2 1 0 • PREV_FBD_ADDR: Base address for preview frame buffer descriptor Written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. The frame buffer is forced to word alignment.
45.4.10 ISI Codec DMA Base Address Register Name: ISI_CDBA Address: 0xFFFC402C Access: Read/Write 31 30 29 28 27 CODEC_DMA_ADDR 26 25 24 23 22 21 20 19 CODEC_DMA_ADDR 18 17 16 15 14 13 12 11 CODEC_DMA_ADDR 10 9 8 7 6 5 4 3 CODEC_DMA_ADDR 2 1 0 • CODEC_DMA_ADDR: Base address for codec DMA This register contains codec datapath start address of buffer location.
45.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register Name: ISI_Y2R_SET0 Address: 0xFFFC4030 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element, default step is 1/128, ranges from 0 to 1.9921875 • C1: Color Space Conversion Matrix Coefficient C1 C1 element, default step is 1/128, ranges from 0 to 1.
45.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register Name: ISI_Y2R_SET1 Address: 0xFFFC4034 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 Cboff 13 Croff 12 Yoff 11 – 10 – 9 – 8 C4 C4 • C4: Color Space Conversion Matrix coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.
45.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register Name: ISI_R2Y_SET0 Address: 0xFFFC4038 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Roff 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375 • C1: Color Space Conversion Matrix coefficient C1 C1 element default step is 1/128, from 0 to 0.
45.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register Name: ISI_R2Y_SET1 Address: 0xFFFC403C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Goff 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 C5 15 14 13 12 C4 7 6 5 4 C3 • C3: Color Space Conversion Matrix coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875 • C4: Color Space Conversion Matrix coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.
45.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register Name: ISI_R2Y_SET2 Address: 0xFFFC4040 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Boff 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 C8 15 14 13 12 C7 7 6 5 4 C6 • C6: Color Space Conversion Matrix coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875 • C7: Color Space Conversion Matrix coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.
46. SAM9263 Electrical Characteristics 46.1 Absolute Maximum Ratings Table 46-1. Absolute Maximum Ratings* Storage Temperature......................................-60°C to 150°C Voltage on Input Pins with Respect to Ground...................................-0.3V to +4.0V Maximum Operating Voltage (VDDCORE and VDDBU)...............................................1.5V *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 46-2. DC Characteristics (Continued) Symbol Parameter VOH Conditions Output High-level Voltage Min Unit VDDIO - 0.4 V CMOS (IO < 0.3 mA), VDDIO 1.65–1.95 V VDDIO - 0.1 V TTL (IO Max), VDDIO 1.65–1.95 V VDDIO - 0.4 V Pull-up Resistance PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31, PE0–PE31 IO Output Current PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31, PE0–PE31 46.3 Max IO Max, VDDIO 3.0–3.6 V RPULLUP ISC Typ On VDDCORE = 1.
Table 46-3. Power Consumption for Different Modes Mode Conditions Consumption Unit ARM Core clock is 198 MHz. MCK is 96 MHz. Dhrystone running in Icache. VDDCORE = 1.08V 55.9 TA = 85°C onto AMP2 ARM Core clock is 240 MHz. MCK is 120 MHz. Full speed Dhrystone running in Icache. (PCK and MCK present) VDDCORE = 1.3V 73.3 mA TA = 85°C onto AMP2 ARM Core clock is 240 MHz. MCK is 120 MHz. Dhrystone running in Icache. VDDCORE = 1.3V 70.9 TA = 25°C onto AMP2 MCK is 96 MHz.
Table 46-3. Power Consumption for Different Modes (Continued) Mode Conditions Consumption Unit ARM Core clock is 500 Hz. MCK is 500 Hz VDDCORE = 1.08V 2720 TA = 85°C onto AMP2 ARM Core clock is 500 Hz. MCK is 500 Hz Quasi Static (system running at 500 Hz) VDDCORE = 1.2V 3080 µA TA = 85°C onto AMP2 ARM Core clock is 500 Hz. MCK is 500 Hz VDDCORE = 1.2V 248 TA = 25°C onto AMP2 VDDBU = 1.08V TA = 85°C 14.8 onto AMP1 VDDBU = 1.2V Backup (in Shutdown Mode) TA = 85°C 16.
Table 46-4. Power Consumption by Peripheral onto AMP2 (TA = 25°C, VDDCORE = 1.2V) Peripheral Consumption AC97 13 CAN 50 EMAC 40 Image Sensor Interface 8 LCDC 45 MCI 13 PIO Controller A or B 5 PIO Controller C to E 14 PWM 7 SPI 9 SSC 16 Timer Counter Channels 8 TWI 2 UDP 9 UHP 12 USART 13 Unit µA/MHz 46.
46.5 Clock Characteristics 46.5.1 Processor Clock Characteristics Table 46-6. Processor Clock Waveform Parameters Symbol Parameter Conditions 1/(tCPPCK) Processor Clock Frequency Min Max VDDCORE = 1.1V; TA = 85°C 200 VDDCORE = 1.3V ± 2%; TA = 85°C 240 Unit MHz 46.5.2 Master Clock Characteristics Table 46-7. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency Conditions Min Max VDDCORE = 1.1V; TA = 85°C 100 VDDCORE = 1.
Table 46-9. Symbol 32 kHz Oscillator Characteristics (Continued) Parameter Conditions Min Typ Max Unit 400 ms 900 ms 600 ms 1200 ms RS = 50 kΩ, CL = 6 pF(1) (1) tSTART RS = 50 kΩ, CL = 12.5 pF Startup Time (1) RS = 100 kΩ, CL = 6 pF (1) Notes: 1. 2. 3. Figure 46-2. RS = 100 kΩ, CL = 12.5 pF RS is the equivalent series resistance, CL is the equivalent load capacitance. CLEXT32 is determined by taking into account internal parasitic and package load capacitance.
Table 46-11. Main Oscillator Characteristics (Continued) Symbol Parameter Conditions IDDST Standby Current Consumption Drive Level PON Min Typ Max Unit Standby mode 1 µA @ 3 MHz 15 @ 8 MHz 30 @ 16 MHz 50 @ 20 MHz Current Dissipation IDD ON Notes: 1. 2. 3. 4. 5. 6. 50 @ 3 MHz(1) 150 250 @ 8 MHz(2) 300 530 300 530 @ 16 MHz µW (3) µA 450 650 @ 20 MHz(4) RS = 100 to 200 Ω ; CSHUNT = 2.0 to 2.5 pF; Cm = 2 to 1.5 fF (typ, worst case) using 1 kΩ serial resistor on XOUT.
46.6.5 PLL Characteristics Table 46-13. Symbol Parameter fOUT Output Frequency fIN Input Frequency IPLL Current Consumption Note: 1. Table 46-14. Min Typ Max Unit Field CKGR_PLLAR.OUTA is 00 80 200 MHz Field CKGR_PLLAR.OUTA is 10 190 240 MHz 1 32 MHz Active mode 3 mA Standby mode 1 µA Max Unit PLLB Characteristics Parameter fOUT Output Frequency fIN Input Frequency IPLL Current Consumption 1. Conditions Startup time depends on PLLA RC filter.
46.8 USB Transceiver Characteristics Table 46-16. Symbol USB Electrical Characteristics Parameter Conditions Min Typ Max Unit 0.8 V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensitivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line Ilkg Hi-Z State Data Line Leakage 0V < VIN < 3.3V REXT Recommended External USB Series Resistor In series with each USB pin with ±5% |(D+) - (D-)| 2.0 V 0.2 V 0.
46.9.2 EBI 0 Timings 46.9.2.1 Read Timings Table 46-18. SMC Read Signals - NRD Controlled (READ_MODE = 1) Parameter Min VDDIOM supply Symbol VDDCORE supply 1.8V 1.08V 3.3V 1.3V 1.08V 1.3V Unit NO HOLD SETTINGS (nrd hold = 0) SMC1 Data Setup before NRD High SMC2 Data Hold after NRD High 16 12.6 15.2 11.9 ns -4.1 -4.1 -3.8 -3.8 ns HOLD SETTINGS (nrd hold ≠ 0) SMC3 Data Setup before NRD High 11.9 9.6 11.3 9.1 ns SMC4 Data Hold after NRD High -3.6 -3.6 -3.3 -3.
Table 46-19. SMC Read Signals - NCS Controlled (READ_MODE = 0) (Continued) Parameter Min VDDIOM supply Symbol SMC14 VDDCORE supply NCS Pulse Width 1.8V 3.3V 1.08V 1.3V 1.08V 1.3V Unit ncs rd pulse length * tCPMCK 0.5 nrd pulse * tCPMCK - 0.4 nrd pulse * tCPMCK - 0.9 nrd pulse * tCPMCK - 0.8 ns 46.9.2.2 Write Timings Table 46-20. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Parameter Min VDDIOM supply Symbol VDDCORE supply Unit 1.8V 1.08V 3.3V 1.3V 1.08V Unit 1.
Table 46-21. SMC Write NCS Controlled (WRITE_MODE = 0) Parameter Min VDDIOM supply Symbol VDDCORE supply Unit 1.8V 3.3V Unit 1.08V 1.3V 1.08V 1.3V SMC22 Data Out Valid before NCS High ncs wr pulse * tCPMCK - 0.6 ncs wr pulse * tCPMCK - 0.3 ncs wr pulse * tCPMCK - 0.9 ncs wr pulse * tCPMCK - 0.5 ns SMC23 NCS Pulse Width ncs wr pulse * tCPMCK - 0.5 ncs wr pulse * tCPMCK - 0.4 ncs wr pulse * tCPMCK - 0.9 ncs wr pulse * tCPMCK - 0.
Table 46-23. SMC Read Signals - NCS Controlled (READ_MODE = 0) Parameter Min VDDIOM supply Symbol VDDCORE supply 1.8V 3.3V 1.08V 1.3V 1.08V 1.3V Unit NO HOLD SETTINGS (ncs rd hold = 0) SMC8 Data Setup before NCS High 16.7 13.1 16.1 12.5 ns SMC9 Data Hold after NCS High -3.2 -3.2 -2.9 -2.9 ns HOLD SETTINGS (ncs rd hold ≠ 0) SMC10 Data Setup before NCS High 13.1 10.5 12.5 9.9 ns SMC11 Data Hold after NCS High -2.8 -2.8 -2.5 -2.
Table 46-24. SM Write Signals - NWE Controlled (WRITE_MODE = 1) (Continued) Parameter Min VDDIOM supply Symbol SMC20 VDDCORE supply NWE High to NCS Inactive (1) 1.8V 1.08V 3.3V 1.3V 1.08V 1.3V (nwe hold - ncs wr (nwe hold - ncs wr (nwe hold - ncs wr (nwe hold - ncs wr hold) * tCPMCK - 1.0 hold) * tCPMCK - 0.7 hold) * tCPMCK - 1.0 hold) * tCPMCK - 0.7 Unit ns NO HOLD SETTINGS (nwe hold = 0) SMC21 Notes: NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25, 2.9 2.9 2.7 2.
Figure 46-4. SMC timings - NCS controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0]/A2-A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 D0 - D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD Figure 46-5.
46.9.4 SDRAMC Signals Timings are given assuming a capacitance load on data, control and address pads as defined in Table 46-26 as well as on the SDCK pad as defined in Table 46-27. Table 46-26. Table 46-27. Capacitance Load on data, control and address pads I/O Supply CLOAD Max 3.3V 50 pF 1.8V 30 pF Capacitance Load on SDCK pad I/O Supply CLOAD Max 3.3V 10 pF 1.8V 10 pF 46.9.4.1 External Bus Interface 0 Timings Table 46-28. SDRAMC Clock Signal Max VDDCORE Supply (VDDIOM 1.
Table 46-29. SDRAMC Signals (Continued) Max VDDCORE Supply (VDDIOM 1.8V) Symbol Parameter SDRAMC14 VDDCORE Supply (VDDIOM 3.3V) 1.08V 1.3V 1.08V 1.3V Unit Bank Change after SDCK Rising Edge 4.6 4.6 5.0 4.2 ns SDRAMC15 CAS Low before SDCK Rising Edge 4.7 4.8 3.0 2.6 ns SDRAMC16 CAS High after SDCK Rising Edge 4.5 4.5 4.9 4.1 ns SDRAMC17 DQM Change before SDCK Rising Edge 2.8 3.2 1.1 0.9 ns SDRAMC18 DQM Change after SDCK Rising Edge 4.2 4.2 4.6 3.
Table 46-31. SDRAMC Signals (Continued) Max VDDCORE Supply (VDDIOM 1.8V) Symbol Parameter SDRAMC8 VDDCORE Supply (VDDIOM 3.3V) 1.08V 1.3V 1.08V 1.3V Unit RAS High after SDCK Rising Edge 3.0 3.4 4.1 3.5 ns SDRAMC9 SDA10 Change before SDCK Rising Edge 4.0 4.3 2.7 2.3 ns SDRAMC10 SDA10 Change after SDCK Rising Edge 3.7 3.8 4.8 3.9 ns SDRAMC11 Address Change before SDCK Rising Edge 3.2 3.6 1.7 1.6 ns SDRAMC12 Address Change after SDCK Rising Edge 3.8 3.9 4.3 3.
Figure 46-6.
46.10 EMAC Timings Table 46-32. EMAC Signals Relative to EMDC Symbol Parameter Min Max Unit EMAC1 Setup for EMDIO from EMDC rising 15.5 ns EMAC2 Hold for EMDIO from EMDC rising -4.4 ns EMAC3 EMDIO toggling from EMDC rising -3.9 3.1 ns Max Unit 46.10.1 MII Mode Table 46-33. 1044 EMAC MII Specific Signals Symbol Parameter Min EMAC4 Setup for ECOL from ETXCK rising -0.4 ns EMAC5 Hold for ECOL from ETXCK rising 2.0 ns EMAC6 Setup for ECRS from ETXCK rising 1.
Figure 46-7. EMAC MII Mode EMDC EMAC1 EMAC3 EMAC2 EMDIO EMAC4 EMAC5 EMAC6 EMAC7 ECOL ECRS ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0] ERXCK EMAC11 EMAC12 ERX[3:0] EMAC13 EMAC14 EMAC15 EMAC16 ERXER ERXDV 46.10.2 RMII Mode Table 46-34. EMAC RMII Specific Signals Symbol Parameter Min Max Unit EMAC21 ETXEN toggling from EREFCK rising 5.0 14.6 ns EMAC22 ETX toggling from EREFCK rising 4.8 12.9 ns EMAC23 Setup for ERX from EREFCK 3.
Figure 46-8. EMAC RMII Mode EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 EMAC24 ERX[1:0] EMAC25 EMAC26 EMAC27 EMAC28 ERXER ECRSDV 46.11 Peripheral Timings 46.11.1 SPI 46.11.1.1 Maximum SPI Frequency The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes. Master Write Mode The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing.
46.11.1.2 Timing Conditions Timings are given assuming a capacitance load on MISO, SPCK and MOSI as defined in Table 46-35. Table 46-35. Capacitance Load for MISO, SPCK and MOSI (product dependent) Supply Max Min 3.3V 40 pF 5 pF 1.8V 20 pF 5 pF 46.11.1.
Figure 46-11. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 46-12. SPI Slave Mode 0 and 3 SPCK SPI6 MISO SPI7 SPI8 SPI10 SPI11 MOSI Figure 46-13. SPI Slave Mode 1 and 2 SPCK SPI9 MISO MOSI Table 46-36. 1048 SPI Timings Symbol Parameter SPI0 MISO Setup time before SPCK rises (master) tCPMCK/2 +10.3 ns SPI1 MISO Hold time after SPCK rises (master) -tCPMCK/2 -3.
Table 46-36. SPI Timings (Continued) Symbol Parameter Conditions Min Max Unit SPI4 MISO Hold time after SPCK falls (master) SPI5 SPCK falling to MOSI Delay (master) 0.4 ns SPI6 SPCK falling to MISO Delay (slave) 9.6 ns SPI7 MOSI Setup time before SPCK rises (slave) 3.5 ns SPI8 MOSI Hold time after SPCK rises (slave) -0.6 ns SPI9 SPCK rising to MISO Delay (slave) SPI10 MOSI Setup time before SPCK falls (slave) 3.4 ns SPI11 MOSI Hold time after SPCK falls (slave) -0.
46.11.3 MCI The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming). These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card. Figure 46-15.
46.11.4 UDP and UHP Switching Characteristics Figure 46-16. USB Data Signal Timing Diagram Rise Time Fall Time 90% VCRS 10% Differential Data Lines 10% tr tf REXT = 27 ohms fosc = 6 MHz/750 kHz Buffer Table 46-41. USB Data Signal Rise and Fall Time Characteristics (Low Speed) Symbol Parameter Conditions tr Transition Rise Time CLOAD = 400 pF tf Transition Fall Time trfm Rise/Fall time Matching Table 46-42.
47. SAM9263 Mechanical Characteristics 47.1 Package Drawing AT91SAM9263B-CU Note: Device AT91SAM9263B-CU is no longer available. Figure 47-1. 324-ball TFBGA Package Drawing Table 47-1. Soldering Information Ball Land 0.4 mm +/- 0.05 Soldering Mask Opening 0.275 mm +/- 0.03 Table 47-2. Device and 324-ball TFBGA Package Maximum Weight 572 Table 47-3. mg 324-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 47-4.
47.1.1 Soldering Profile Table 47-10 gives the recommended soldering profile from J-STD-020C. Table 47-5. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260 +0 °C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
47.2 Package Drawing AT91SAM9263B-CU-100 Figure 47-2. 324-ball TFBGA Package Drawing Table 47-6. Soldering Information Ball Land 0.4 mm +/- 0.05 Solder Mask Opening 0.275 mm +/- 0.03 Table 47-7. Device and 324-ball TFBGA Package Maximum Weight 572 Table 47-8. mg 324-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 47-9. 3 Package Reference JEDEC Drawing Reference MO-275 JESD97 Classification e8 This package respects the recommendations of the NEMI User Group.
47.2.1 Soldering Profile Table 47-10 gives the recommended soldering profile from J-STD-020D. Table 47-10. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 60 sec. to 120 sec Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260 +0°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
48. Marking All devices are marked with the Atmel logo and the ordering code.
49. SAM9263 Ordering Information Table 49-1.
50. SAM9263 Errata 50.1 SAM9263 Errata - Revision “B” Parts 50.1.1 Main Oscillator 50.1.1.1 Main Oscillator: Spurious Malfunction of Main Oscillator The main oscillator can exhibit spurious malfunction as exhibited by the duty-cycle not performing according to specification, missing main clock periods, or in the worst case, no main clock at all. The behavior does not alter over time.
50.1.5 CAN 50.1.5.1 CAN: Low Power Mode and Error Frame If the Low Power Mode is activated while the CAN is generating an error frame, this error frame may be shortened. Problem Fix/Workaround None 50.1.5.2 CAN: Low Power Mode and Pending Transmit Messages No pending transmit messages may be sent once the CAN Controller enters Low-power Mode. Problem Fix/Workaround Check that all messages have been sent by reading the related Flags before entering Low-power Mode. 50.1.5.
EMACB master interface releases the AHB bus between two transfers. EMACB has the highest priority. If we are in a state where EMACB RX and TX FIFOs have requests pending, the following sequence occurs: 1. EMACB RX FIFO write (burst 4) 2. EMACB release the AHB bus 3. The AHB matrix can grant an another master (ARM I or D for example) 4. AHB matrix re-arbitration (finish at least the current word/halfword/byte) 5. The AHB matrix grants the EMACB 6.
DMA Base Address must be programmed with a value aligned onto LCD DMA burst size. e.g.: BRSTLN = 15 For a 16-word burst, the LCD DMA Base Address must start on 16-word offset: 0x0, 0x40, 0x80 or 0xc0. BRSTLN = 3 For a 4-word burst, the LCD DMA Base Address must start on 0x0, 0x10, ..., 0xf0. 50.1.8.3 24-bit Packed Mode LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed mode. A 32-bit word contains some bits of a pixel and some bits of the following pixel.
50.1.9.4 Data Write Operation and Number of Bytes The Data Write operation with a number of bytes less than 12 is impossible. Problem Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number. 50.1.9.5 Flag Reset is not correct in half duplex mode In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect.
Example with libV3.
STR r1, [r0] ;perform proc_reset and periph_reset (in the ARM pipeline) STR r3, [r2] END 50.1.12 SDRAM Controller 50.1.12.1 Mobile SDRAM Device Initialization Constraint Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM device initialization may lead to data bus contention and thus external memories on the same EBI must not be accessed. This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this phase.
50.1.14.4 SPI: Baudrate Set to 1 When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency), and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No such pulse occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None. 50.1.14.
50.1.15.3 Unexpected Delay on TD output When SSC is configured with the following conditions: TCMR.STTDLY more than 0 RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge RFMR.FSOS = None (input) TCMR.START = Receive Start An unexpected delay of two or three system clock cycles is added to TD output. Problem Fix/Workaround None. 50.1.16 Pulse Width Modulation (PWM) 50.1.16.1 Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register.
50.1.18.4 STOP not Generated If the sequence described as follows occurs: 1. WRITE 1 or more bytes at a given address. 2. Send a STOP. 3. Wait for TXCOMP flag. 4. READ (or WRITE) 1 or more bytes at the same address. The STOP is not generated. The line shows: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n. Problem Fix/Workaround Insert a delay of one TWI clock period before step 4. 50.1.19 UDP 50.1.19.
50.1.20.2 ISO OUT Transfers Conditions: Consider the following scenario: 1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory. 2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the packet are not available. This results in a buffer underrun condition. 3. While there is an underrun condition, if the Host controller is in the process of bit-stuffing, it causes the Host controller to hang.
50.1.21.3 Two characters sent if CTS rises during emission If CTS rises to 1 during a character transmit, the Transmit Holding Register is also transmitted if not empty. Problem Fix/Workaround None. 50.1.21.4 TXD signal is floating in Modem and Hardware Handshaking mod TXD signal should be pulled up in Modem and Hardware Handshaking mode. Problem Fix/Workaround TXD is multiplexed with PIO which integrates a pull up resistor. This internal pull-up must be enabled. 50.1.21.
51. Revision History The most recent version appears first in the tables that follow. The initials “rfo” indicate changes requested by product experts, or made during proof reading as part of the approval process. Table 51-1. Revision History - SAM9263 Datasheet Revision 6249N Date Comments Section “Description”: “Two D Graphics Controller” changed to “Two D Graphics Accelerator” Section 4. “Power Considerations” Section 4.2.
Table 51-2. Revision History - SAM9263 Datasheet Revision 6249M Date Comments General formatting and editorial changes throughout Changed several instances of “AT91SAM9263” to “SAM9263” Throughout, instances of “32768 Hz” changed to “32.768 kHz” “Features” Deleted bullet “Required Power Supplies” Section 1. “SAM9263 Block Diagram” Section 1-1 “SAM9263 Block Diagram”: labeled “Backup Section”; updated oscillator naming Section 4. “Power Considerations” Added Section 4.
Table 51-2. Revision History - SAM9263 Datasheet Revision 6249M (Continued) Date Comments Section 16. “Watchdog Timer (WDT)” Added Section 16.2 “Embedded Characteristics” Section 17. “Shutdown Controller (SHDWC)” Added Section 17.2 “Embedded Characteristics” Section 19. “SAM9263 Bus Matrix” Table 19-1 “Register Mapping”: removed reset value from write-only registers Removed reset value from Section 19.5.
Table 51-2. Revision History - SAM9263 Datasheet Revision 6249M (Continued) Date Comments Section 29. “Debug Unit (DBGU)” Added Section 29.2 “Embedded Characteristics” Table 29-2 “Register Mapping”: - added reset value 0x00181800 for DBGU_SR - added reset value 0x019607A0 for DBGU_CIDR Section 32. “Two-wire Interface (TWI)” Table 32-4 “Register Mapping”: for TW_THR, access “Read-write” corrected to “Write-only” and reset value removed Section 32.9.
Table 51-2. Revision History - SAM9263 Datasheet Revision 6249M (Continued) Date Comments Section 44. “Two D Graphics Controller (TDGC)” (cont’d) Removed reset value from register description sections (reset values are provided in Table 44-2 “TDGC Register Mapping”) Section 45.
Revision 6249L Change Request Ref. Comments AT91SAM9263 Boot Program: 7643 Section 12.6 “NAND Flash Boot”, added a phrase in the 1st paragraph. PMC: Section 27.7 “Programming Sequence”, updated PMC_MCKR programming sequence in Step 5. 8858 TWI: Updated sections: Section 32.1 “Description” Section 32.2 “Embedded Characteristics” 6231 Section 32.7.1 “I/O Lines” Section 32.8 “Functional Description” Section 32.
Revision 6249J Comments Change Request Ref. Overview: Section 5.3 “Reset Pins”, removed line “The NRST signal is inserted in the Boundary Scan.” 6783 CAN: Figure 36-7, TEC and REC parameters to pass from and to “ERROR ACTIVE” to “ERROR PASSIVE” interchanged. Electrical Characteristics: 7511 6872 Table 46.11.1 “SPI”, simplified figure titles. The new titles are as follows: Table 46.11.1.
Revision 6249I Change Request Ref. Comments Electrical Characteristics: Table 46-3 “Power Consumption for Different Modes” edited: VDDCORE 1.2V --> 1.3V. Table 46-6 “Processor Clock Waveform Parameters” and Table 46-7 “Master Clock Waveform Parameters” edited: VDDCORE 1.2V --> 1.3V ± 2%. Back page: rfo Latest back page file used. Revision 6249H 7345 Change Request Ref.
Revision 6249G Comments Change Request Ref. Overview: Section “Features” Debug Unit (DBGU) updated. 5846 Section 9.4.3 “EBI1”, updated 5903 Section 9.4.4 “Ethernet 10/100MAC”, added to datasheet Section 5.5 “Shutdown Logic Pins”, updated, “SHDN pin is tri state output.......” rfo BootProgram: Section 12.5 “SD Card Boot” Boot ROM does not support high capacity SDCards, added to datasheet Section 12.
Revision 6249F Change Request Ref. Comments Section 5.1 ”Power Supplies”, VDDCORE and VDDBU updated. Section 5.2, “Power Sequence Requirements removed from datasheet. 5791/5793 USART: Section 33.5.1 “I/O Lines”, reference to modem mode removed. 5743 Section 33.3 “Application Block Diagram”, updated and modem removed Revision 6249E Change Request Ref. Comments Overview: New Ordering Code: AT91SAM9263B-CU added to Table 49-1 “SAM9263 Ordering Information”. 5560 Section 8.1.2.
Revision 6249E Comments (Continued) Change Request Ref. DMAC: Figure 24-4, “External DMA Request Timing,” on page 266, updated. 5503 Section “External DMA Request Definition”, 3rd paragraph CTLxL.xxx typos fixed. “The DMA ends...” added to 4th paragraph. rfo Multiple bits represented by “x” in Bit names from Section 24.4.11 on page 305 to Section 24.4.23 on page 317 5504 Section 24.4.7 “Configuration Register for Channel x High”, SRC_PER bitfield description unscrambled from previous paragraph.
Revision 6249E Change Request Ref. Comments (Continued) SDRAMC: Section 22.6.1 “SDRAMC Mode Register”; changed MODE bit description. 4593 SDRAMC Configuration Register “CAS: CAS Latency” on page 242, changed CAS bit description 4623 SHDWC: Table 17-1 “Shutdown Controller Block Diagram”; corrected register names in the block diagram. 4734 SMC: Section 22.14 ”Programmable IO Delays”, added to datasheet rfo/4951 Section 21.8.
Revision 6249E Comments (Continued) Table 42-4 “Register Mapping”, UDP_CSR, UDP_FDR updated with indexed offsets. Footnote added to UDP_ISR reset Change Request Ref. 4802 Section 42.6.6 “UDP Interrupt Mask Register”, bit 12 defined as BIT12, cannot be masked. Section 42.6 “USB Device Port (UDP) User Interface”, reset value for UDP_RST_EP is 0x0000_0000 TXCV typo fixed to TXVC. Table 42-1 “USB Endpoint Description”, footnote added to Dual-Bank heading 5049 5150 Section 42.5.2.
Revision 6249D Change Request Ref. Comments Overview: ”Features” SPI: Synchronous Communications feature removed. 4910 Section 5.1 ”Power Supplies”, VDDIO and VDDBU slope alignment described. 4967 Section 5.2 ”Power Consumption”, paragraph beginning with “On VDDBU...” updated. 4505 Section 10.5.8 ”Multimedia Card Interface”,”When REMAP = 1.....” removed from 2nd paragraph. 5029 Section 8.2.1.1 ”External Bus Interface 0”, feature added. 4146 Section 8.2.1.
Revision 6249D Comments Change Request Ref. ”SAM9263 Errata” (continued) 1084 ”Serial Synchronous Controller (SSC)”, Section 50.1.16.3 ”SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer” and Section 50.1.16.4 ”SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer”, added. 4771 ”USART”, Section 50.1.21.4 ”Two characters sent if CTS rises during emission”, added. 4692 Section 50.1.21.5 ”TXD signal is floating in Modem and Hardware Handshaking mod” and Section 50.
Revision 6249C Comments Change Request Ref. In Section 4.1 “324-ball TFBGA Package Outline” on page 10 corrected package top view. 4463 All new information for Table 7-1, “List of Bus Matrix Masters,” on page 16, Table 7-2, “List of Bus Matrix Slaves,” on page 17 and Table 7-3, “Masters to Slaves Access,” on page 18. 4466 In Section 9.3 “Shutdown Controller” on page 29, corrected reference to shutdown pin. 3870 In Section 5.
Revision 6249C Comments USART: In Section 33.5.1 “I/O Lines” on page 515 added information on TXD enabled. Change Request Ref. 4825 In Section 33.6.2 “Receiver and Transmitter Control” on page 521, corrected information on software reset. 4367 CAN: In Figure 36-7 on page 642 corrected mode switch conditions. 4089 3476 UDP: Table 42-2 on page 856, “Supported Endpoint” column updated in the USB Communication Flow.
Revision 6249B Revision 6249A Comments Change Request Ref. Corrected typo to IDE hard disk in Section 1. ”Description”, on page 3. 3804 In Section 12. “SAM9263 Boot Program” on page 96, added information on NAND Flash and SDCard boot in the ROM. 3802 Corrected typo in PB range in Table 46-2, “DC Characteristics,” on page 983. Updated Static Current conditions and values. 3804 Corrected ordering code in Section 48. ”AT91SAM9263 Ordering Information”, on page 1017.
Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. SAM9263 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.
9. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1 9.2 9.3 9.4 9.5 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.5 Periodic Interval Timer (PIT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 16. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.1 16.2 16.3 16.4 16.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . .
21.14 Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 22. SDRAM Controller (SDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 22.1 22.2 22.3 22.4 22.5 22.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . .
28.7 28.8 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Advanced Interrupt Controller (AIC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 29. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 29.1 29.2 29.3 29.4 29.5 29.6 Description . . . . . . . . . . . . . . . . . . .
34.4 34.5 34.6 34.7 34.8 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 SSC Application Examples . . . . . . . . . . . . . .
39.10 MultiMedia Card Interface (MCI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 40. Ethernet MAC 10/100 (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 40.1 40.2 40.3 40.4 40.5 40.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 Embedded Characteristics . . . . . . . . . . . . . . . . .
46. SAM9263 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 46.1 46.2 46.3 46.4 46.5 46.6 46.7 46.8 46.9 46.10 46.11 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . .
ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd.
