Datasheet

91
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
13.4.4.2 Wakeup Reset
The Wakeup Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the
reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is
resynchronized on Slow Clock. The processor clock is then re-enabled during 2 Slow Clock cycles, depending on
the requirements of the ARM processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to
report a Wakeup Reset.
The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed up, the
programmed number of cycles is applicable.
When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is
synchronous with the output of the Main Supply POR.
Figure 13-5. Wakeup State
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 4 cycles (ERSTL = 1)
MCK
Processor Startup
= 2 cycles
backup_nreset
Any
Freq.
Resynch.
2 cycles
RSTTYP
XXX 0x1 = WakeUp Reset
XXX