Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
86
The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must
be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at
boot time, and electrical conflicts between SPI output pins and the connected devices may appear.
To assure correct functionality, it is recommended to plug in critical devices to other pins.
Table 12-5 contains a list of pins that are driven during the boot program execution. These pins are driven during
the boot sequence for a period of less than 1 second if no correct boot program is found.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot
program are set to their reset state.
Table 12-5. Pins Driven During Boot Program Execution
Peripheral Pin PIO Line
SPI0 MOSI PIOA1
SPI0 MISO PIOA0
SPI0 SPCK PIOA2
SPI0 NPCS0 PIOA3
PIOC NANDCS PIOC14
PIOC NAND OE PIOC0
PIOC NAND WE PIOC1
Address Bus NAND CLE A21
Address Bus NAND ALE A22
MCI0 MCDA0 PIOA0
MCI0 MCCDA PIOA1
MCI0 MCCK PIOA2
MCI0 MCDA1 PIOA4
MCI0 MCDA2 PIOA5
MCI0 MCDA3 PIOA6
TWI TWCK PIOA8
TWI TWD PIOA7
DBGU DRXD PIOA9
DBGU DTXD PIOA10