Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
740
Doc. Rev.
6062B
Date
14-Oct-05 Comments
Change
Request
Reference
Changed SPI pin names in Figure 2-1, “AT91SAM9261 Block Diagram,” on page 4,
Table 3-1, “Signal Description by Peripheral,” on page 5, Table 10-1, “Multiplexing on PIO
Controller A,” on page 30, Table 10-2, “Multiplexing on PIO Controller B,” on page 31 and
Table 10-3, “Multiplexing on PIO Controller C,” on page 32.
05-398
Corrected EBI/Compact Flash interface description with updated A22 pin functionality in
Figure 2-1, “AT91SAM9261 Block Diagram,” on page 4, Figure 20-1, “Organization of the
External Bus Interface,” on page 131 and Table 20-6, “CFCE1 and CFCE2 Truth Table,” on
page 139.
05-481
Changed value of programmable pull-up resistor in Section 6.4 ”PIO Controller A, B and C
Lines” on page 12.
05-496
Bus Matrix: Corrected reset values of Slave Configuration Registers 0, 1 and 2 in Table 18-
1, “Register Mapping,” on page 125.
05-498
Bus Matrix: Updated bit information in Section 18.5.5 “USB Pad Pull-up Control Register”
on page 130.
05-486
SMC: Corrected reset values of SMC_SETUP, SMC_CYCLE and SMC_MODE in
Table 21-9, “SMC Register Mapping,” on page 181.
05-499
SDRAMC: Removed Hardware Interface section from Section 22.4 ”Application Example”
on page 188.
05-468
SDRAMC: Updated Figure 22-2, “SDRAM Device Initialization Sequence,” on page 191. 05-479
PMC: Updated Section 25.8 ”Programming Sequence” on page 229. 05-393
PMC: Updated Figure 25-5, “Change PLLA Programming,” on page 235 and added
Figure 25-6, “Change PLLB Programming,” on page 235.
05-198
PMC: Added important note on programming Bit 29 of CKGR_PLLAR in Section 25.8
”Programming Sequence” on page 229 and in Section 25.10.9 ”PMC Clock Generator PLL
A Register” on page 245.
05-239
AIC: Added information on external interrupt sources for bit SRCTYPE in Section 26.8.3
”AIC Source Mode Register” on page 267.
05-269
DBGU: Updated bit description for SRAMSIZ in Section 27.5.10 ”Debug Unit Chip ID
Register” on page 300.
05-306
PIO: Removed reference to resistor value in Section 28.4.1 ”Pull-up Resistor Control” on
page 331.
05-497
SPI: References to MCK/32 removed throughout. Figure 29-1, “Block Diagram,” on
page 338 and Figure 29-5, “Master Mode Block Diagram,” on page 343 changed.
05-484
SPI: Section 29
.7
.5 ”SPI Status Register” on page 356 SPI_RCR, SPI_RNCR, SPI_TCR,
SPI_TNCR location defined.
04-183
SPI: Section 29.7.4 ”SPI Transmit Data Register” on page 355, LASTXFER: Last Transfer
text added.
05-434
SPI: Section 29.7.2 ”SPI Mode Register” on page 352, PCSDEC: Chip Select Decode on
changed
05-476
MCI: Corrected pin names in Figure 34-4, “MMC Bus Connections (One Slot),” on
page 498.
05-308
UHP: Added information on memory access errors in “USB Host Port (UHP)” on page 522. 05-240
LCDC: Inserted FIFO size in ”FIFO” on page 564 and in Section 37.10.14 ”LCD FIFO
Register” on page 598.
05-381