Datasheet

737
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
Doc. Rev.
6062D
Date
14-Apr-06 Comments
Change
Request
Reference
Updated information on JTAGSEL in Section 3-1 ”Signal Description by Peripheral” on
page 5 and in Section 6.1 ”JTAG Port Pins” on page 11.
2946
Reformatted Section 8. ”Memories” on page 16. Inserted new Figure 8-1, “AT91SAM9261
Memory Mapping,” on page 16 to show full product memory mapping.
2475
Inserted new Section 8.1.2 ”Boot Strategies” on page 20 to replace Boot ROM section. 2480
Removed information on Timer Counter clock assignments in Section 10.11 ”Timer
Counter” on page 37.
2474
In section Debug and Test, added Section 11.5.3 “JTAG Signal Description” on page 57. 2557
RSTC: In Section 14.3.1 ”Reset Controller Overview” on page 95, added information on
startup counter.
3005
RTT: Added note to Section 14.4 “Functional Description” giving information on
asynchronism between SCLK and MCK.
2522
SHDWC: In Section 18.5 ”Functional Description” added “The shutdown is taken into
account only 2 slow clock cycles after the write of SHDW_CR.”
2549
Bus Matrix: Removed bits RCB4, RCB3 and RCB2 from MATRIX_MCFG in Section 18.5.1
“Bus Matrix Master Configuration Register” on page 126.
2731
EBI: Added Section 19.7 “Implementation Examples” on page 145.
PMC: Updated OUTx bit descriptions in Section 25.10.9 ”PMC Clock Generator PLL A
Register” on page 270 and Section 25.10.10 ”PMC Clock Generator PLL B Register” on
page 271.
2467
PMC: Added note defining PIDx in Section 25.10.4 ”PMC Peripheral Clock Enable
Register” on page 266, Section 25.10.5 ”PMC Peripheral Clock Disable Register” on page
266 and Section 25.10.6 ”PMC Peripheral Clock Status Register” on page 267.
2468
PMC: Updated document to with details on oscillator selection. Added bit OSCSEL to
Section 25.10.15 ”PMC Status Register” on page 275.
2558
PMC: Addition of PLL Charge Pump Current Register in Table 25-3, “Register Mapping,”
on page 262 and Section 25.10.17 ”PLL Charge Pump Current Register” on page 277.
2568
AIC: Section 26.7.3.1 “Priority Controller” on page 276, incorrect reference of SRCTYPE
field to AIC_SVR register changed to AIC_SMR register.
2512
AIC: Section 26.8 “Advanced Interrupt Controller (AIC) User Interface” on page 282, Table
26-2 added note in reference to PID2...PID31 bit fields.
2548
AIC: Naming convention for AIC_FVR registe
r harmonized in Table 26-2, “Register
Mapping,” on page 282 and “Fast Forcing” on page 279.
2524
DBGU: In Figure 27-1, “Debug Unit Functional Block Diagram,” on page 304, changed
signal ice_reset to pad Power_on Reset. Also changed in bit description FNTRST in
Section 27.5.12 ”Debug Unit Force NTRST Register” on page 325.
USART: MANE bit removed from Section 31.7.3 ”USART Interrupt Enable Register” on
page 432.
2747
USART: Section 31.5.1 ”I/O Lines” on page 402, text concerning TXD line added.
Table 31-3, “Binary and Decimal Values for Di,” on page 406 and Table 31-4, “Binary and
Decimal Values for Fi,” on page 406 DI and Fi properly referenced in titles.
Figure 31-24, “IrDA Demodulator Operations,” on page 422 modified.
2794
TC: Addition of Table 33-1, “Timer Counter Clock Assignment,” on page 483. 2470