Datasheet

729
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
LCDC:
Table 37-1 “I/O Lines Description”, updated description of LCDDEN. 3587
Section 37.5.1.3 “Channel-U”, Removed equations for STN Monochrome mode and STN Color
mode. Updated definitions.
Table 37-4 “Big Endian Memory Organization”, Inverted Pixel 1bpp row values to go from 0 to 31.
Section 37.10.23 “Power Control Register”, LCD_PWR bit description, changed all occurences of
“pin” to “signal”.
4268
Section 37.10.1 “DMA Base Address Register 1”, updated with new values for bits 0 and 1. 4488
Section 37.5.2.7 “Shifter”, fixed typo: “LDCCON3 register” corrected to read “LCDCON2 register” 4739
Section 37.9.2 “TFT Mode Example”, HFP = (16-2), HBP = (48 -1), HPW = (64-1), typo corrected. 5619
”Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is
configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2) LCDDOTCK
cycles.” on page 632.
HFP+2 (not HFP+1) idem for
Section 37.10.12 “LCD Timing Configuration Register 2”
and the timing diagrams
Figure 37-3 ”STN Panel Timing, CLKMOD 0”
Figure 37-4 ”TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1”
Figure 37-5 ”TFT Panel Timing (Line Expanded View), CLKMOD=1”
rfo
PMC:
Section 24.1 “Overview”
 PCK must be switched off when entering processor in Idle Mode.
Section 24.3 “Processor Clock Controller”, updated with information on “Wait for Interrup Mode”.
4322
Figure 23-1 ”Typical Slow Clock Crystal Oscillator Connection”, GNDPLL changed to GNDBU. 4470
Section 24.7 “Programming Sequence”, correction to Step 5, and Step 6, “....PRES parameter is set
to 0...”
5596
Doc. Rev.
6062K
Date
27-Aug-08 Comments (Continued)
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