Datasheet

SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
724
21-Jun-16
Section 12. “Boot Program” (cont’d)
Section 12.10.3 “USB Device Port”: deleted reference to “Windows XP”
Section 12.11 “Hardware and Software Constraints”: added note “Boot ROM does not support high capacity
SDCards.”
Section 13. “Reset Controller (RSTC)”
Added Section 13.2 “Embedded Characteristics”
Section 14. “Real-time Timer (RTT)”
Added Section 14.2 “Embedded Characteristics”
Section 15. “Periodic Interval Timer (PIT)”
Added Section 15.2 “Embedded Characteristics”
Section 16. “Shutdown Controller (SHDWC)”
Added Section 16.2 “Embedded Characteristics”
Section 18. “Bus Matrix”
Removed reset value from Section 18.5.3 “Bus Matrix TCM Configuration Register”, Section 18.5.4 “EBI Chip Select
Assignment Register” and Section 18.5.5 “USB Pad Pull-up Control Register” (reset values are provided in Table 18-
1 “Register Mapping”)
Table 18-1 “Register Mapping”: removed reset value from MATRIX_MCFG (register is write-only)
Section 19. “External Bus Interface (EBI)”
Section 19.6.5.2 “CFCE1 and CFCE2 Signals”: “The Chip Select Register (DBW field in the corresponding Chip
Select Register) of the NCS4” corrected to “The DBW field in the SMC Mode Register corresponding to the NCS4”
Section 20. “Static Memory Controller (SMC)”
Updated Section 20.8.1.3 “Read Cycle” and Section 20.8.3.3 “Write Cycle”
Updated Section 20.8.6 “Reset Values of Timing Parameters”
Section 20.13.2 “Byte Access Type in Page Mode”: “SMC_REGISTER” corrected to “SMC Mode Register”
Section 21. “SDRAM Controller (SDRAMC)”
Table 21-8 “Register Mapping”: access “Read” corrected to “Read/Write” for SDRAMC_MDR
Removed reset value from Section 21.6.1 “SDRAMC Mode Register”, Section 21.6.2 “SDRAMC Refresh Timer
Register”, Section 21.6.3 “SDRAMC Configuration Register”, and Section 21.6.4 “SDRAMC Low Power Register”
(reset values are provided in Table 21-8 “Register Mapping”)
Section 22. “Peripheral DMA Controller (PDC)”
Table 22-1 “Register Mapping”: removed reset value from PERIPH_PTCR (register is write-only)
Section 24. “Power Management Controller (PMC)”
Section 24.7 “Programming Sequence”: updated Step 5 “Selection of Master Clock and Processor Clock”
Table 24-3 “Register Mapping”: access for PMC_PLLICPR changed from “Write-only” to “Read/Write”
Section 24.9.17 “PLL Charge Pump Current Register”: access changed from “Write-only” to “Read/Write”
Section 25. “Watchdog Timer (WDT)”
Added Section 25.2 “Embedded Characteristics”
Section 26. “Advanced Interrupt Controller (AIC)”
Table 26-2 “Register Mapping”: deleted footnote “Values in the Version Register vary with the version of the IP block
implementation.”
Removed reset value from register description sections (reset values are provided in Table 26-2 “Register Mapping”)
Table 43-1. Revision History - SAM9261 Datasheet Revision 6082O
Date Comments