Datasheet

721
SAM9261 [DATASHEET]
Atmel-6062O-ATARM-SAM9261-Datasheet_21-Jun-16
42.2.15.6 TWI: STOP not generated
If the sequence described as follows occurs:
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
then STOP is not generated.
The line will show: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Problem Fix/Workaround
Insert a delay of one TWI clock period before step 4 in the sequence above.
42.2.16 UDP
42.2.16.1 UDP: Bad data in the first IN data stage
All or part of the data of the first IN data Stage are not transmitted.It may then be a Zero Length Packet. The CRC
is correct. So the HOST may only see that the size of the received data does not match the requested length. But
even if performed again, the control transfer will probably fail.
Problem Fix/Workaround
These Control transfers are mainly used at device configuration. After clearing RXSETUP, the software needs to
compute the setup transaction request before writing data into the FIFO if needed. This time is generally greater
than the minimum safe delay required above. If not, a software wait loop after RXSETUP clear may be added at
minimum cost
42.2.17 UHP
42.2.17.1 UHP: Non-ISO IN transfers
Conditions:
Consider the following sequence:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement
write) to the system memory in order to complete the status update.
5. The Host controller raises the request for the first write transaction. By the time the transaction is completed,
a frame boundary is crossed.
6. After completing the first write transaction, the Host controller skips the second write transaction.
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN token.
Problem Fix/Workaround
This problem can be avoided if the system guarantees that the status update can be completed within the same
frame.
42.2.17.2 UHP: ISO OUT transfers
Conditions:
Consider the following sequence:
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory.
2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the
packet are not available. This results in a buffer underrun condition.